src/southbridge/via/k8t890/host_ctrl.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
   5  * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me@gmail.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  19  */
  20
  21 #include <device/device.h>
  22 #include <device/pci.h>
  23 #include <device/pci_ops.h>
  24 #include <device/pci_ids.h>
  25 #include <console/console.h>
  26 #include <cbmem.h>
  27 #include <arch/io.h>
  28 #include "k8x8xx.h"
  29
  30 /* this may be later merged */
  31
  32 /* This fine tunes the HT link settings, which were loaded by ROM strap. */
  33 static void host_ctrl_enable_k8t8xx(struct device *dev)
  34 {
  35         /*
  36          * Bit 4 is reserved but set by AW. Set PCI to HT outstanding
  37          * requests to 3.
  38          */
  39         pci_write_config8(dev, 0xa0, 0x13);
  40
  41         /*
  42          * NVRAM I/O base at K8T890_NVRAM_IO_BASE
  43          * Some bits are set and reserved.
  44          */
  45         pci_write_config8(dev, 0xa2, (K8T890_NVRAM_IO_BASE >> 8));
  46
  47         /* enable NB NVRAM and enable non-posted PCI writes. */
  48         pci_write_config8(dev, 0xa1, 0x8f);
  49         /* Arbitration control, some bits are reserved. */
  50         pci_write_config8(dev, 0xa5, 0x3c);
  51
  52         /* Arbitration control 2 */
  53         pci_write_config8(dev, 0xa6, 0x80);
  54
  55         /* this will be possibly removed, when I figure out
  56          * if the ROM SIP is good, second reason is that the
  57          * unknown bits are AGP related, which are dummy on K8T890
  58          */
  59
  60         writeback(dev, 0xa0, 0x13);     /* Bit4 is reserved! */
  61         writeback(dev, 0xa1, 0x8e);     /* Some bits are reserved. */
  62         writeback(dev, 0xa2, 0x0e);     /* I/O NVRAM base 0xe00-0xeff disabled. */
  63         writeback(dev, 0xa3, 0x31);
  64         writeback(dev, 0xa4, 0x30);
  65
  66         writeback(dev, 0xa5, 0x3c);     /* Some bits reserved. */
  67         writeback(dev, 0xa6, 0x80);     /* Some bits reserved. */
  68         writeback(dev, 0xa7, 0x86);     /* Some bits reserved. */
  69         writeback(dev, 0xa8, 0x7f);     /* Some bits reserved. */
  70         writeback(dev, 0xa9, 0xcf);     /* Some bits reserved. */
  71         writeback(dev, 0xaa, 0x44);
  72         writeback(dev, 0xab, 0x22);
  73         writeback(dev, 0xac, 0x35);     /* Maybe bit0 is read-only? */
  74
  75         writeback(dev, 0xae, 0x22);
  76         writeback(dev, 0xaf, 0x40);
  77         /* b0 is missing. */
  78         writeback(dev, 0xb1, 0x13);
  79         writeback(dev, 0xb4, 0x02);     /* Some bits are reserved. */
  80         writeback(dev, 0xc0, 0x20);
  81         writeback(dev, 0xc1, 0xaa);
  82         writeback(dev, 0xc2, 0xaa);
  83         writeback(dev, 0xc3, 0x02);
  84         writeback(dev, 0xc4, 0x50);
  85         writeback(dev, 0xc5, 0x50);
  86
  87         print_debug(" VIA_X_2 device dump:\n");
  88         dump_south(dev);
  89 }
  90
  91 /* This fine tunes the HT link settings, which were loaded by ROM strap. */
  92 static void host_ctrl_enable_k8m8xx(struct device *dev) {
  93
  94         /*
  95          * Set PCI to HT outstanding requests to 03.
  96          * Bit 4 32 AGP ADS Read Outstanding Request Number
  97          */
  98         pci_write_config8(dev, 0xa0, 0x13);
  99
 100         /*
 101          * NVRAM I/O base at K8T890_NVRAM_IO_BASE
 102          */
 103
 104         pci_write_config8(dev, 0xa2, (K8T890_NVRAM_IO_BASE >> 8));
 105
 106         /* Enable NVRAM and enable non-posted PCI writes. */
 107         pci_write_config8(dev, 0xa1, 0x8f);
 108
 109         /* Arbitration control  */
 110         pci_write_config8(dev, 0xa5, 0x3c);
 111
 112         /* Arbitration control 2, Enable C2NOW delay to PSTATECTL */
 113         pci_write_config8(dev, 0xa6, 0x83);
 114
 115 }
 116 #if 0
 117 struct cbmem_entry *get_cbmem_toc(void) {
 118                 return (struct cbmem_entry *) inl(K8T890_NVRAM_IO_BASE+K8T890_NVRAM_CBMEM_TOC);
 119 }
 120 #endif
 121 void set_cbmem_toc(struct cbmem_entry *toc) {
 122                 outl((u32) toc, K8T890_NVRAM_IO_BASE+K8T890_NVRAM_CBMEM_TOC);
 123 }
 124
 125 static const struct device_operations host_ctrl_ops_t = {
 126         .read_resources         = pci_dev_read_resources,
 127         .set_resources          = pci_dev_set_resources,
 128         .enable_resources       = pci_dev_enable_resources,
 129         .enable                 = host_ctrl_enable_k8t8xx,
 130         .ops_pci                = 0,
 131 };
 132
 133 static const struct device_operations host_ctrl_ops_m = {
 134         .read_resources         = pci_dev_read_resources,
 135         .set_resources          = pci_dev_set_resources,
 136         .enable_resources       = pci_dev_enable_resources,
 137         .enable                 = host_ctrl_enable_k8m8xx,
 138         .ops_pci                = 0,
 139 };
 140
 141 static const struct pci_driver northbridge_driver_t800 __pci_driver = {
 142         .ops    = &host_ctrl_ops_t,
 143         .vendor = PCI_VENDOR_ID_VIA,
 144         .device = PCI_DEVICE_ID_VIA_K8T800_HOST_CTR,
 145 };
 146
 147 static const struct pci_driver northbridge_driver_m800 __pci_driver = {
 148         .ops    = &host_ctrl_ops_m,
 149         .vendor = PCI_VENDOR_ID_VIA,
 150         .device = PCI_DEVICE_ID_VIA_K8M800_HOST_CTR,
 151 };
 152
 153 static const struct pci_driver northbridge_driver_t890 __pci_driver = {
 154         .ops    = &host_ctrl_ops_t,
 155         .vendor = PCI_VENDOR_ID_VIA,
 156         .device = PCI_DEVICE_ID_VIA_K8T890CE_2,
 157 };
 158
 159 static const struct pci_driver northbridge_driver_m890 __pci_driver = {
 160         .ops    = &host_ctrl_ops_m,
 161         .vendor = PCI_VENDOR_ID_VIA,
 162         .device = PCI_DEVICE_ID_VIA_K8M890CE_2,
 163 };