src/southbridge/via/k8t890/host.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
   5  * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me@gmail.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  19  */
  20
  21 #include <device/device.h>
  22 #include <device/pci.h>
  23 #include <device/pci_ops.h>
  24 #include <device/pci_ids.h>
  25 #include <console/console.h>
  26 #include "k8x8xx.h"
  27
  28 static void host_old_enable(struct device *dev)
  29 {
  30         int agp3;
  31
  32         /* some HT tweaking */
  33         pci_write_config8(dev, 0x50, 0x03);
  34         pci_write_config8(dev, 0x55, 0x2c);
  35
  36         /* AGP setup */
  37         pci_write_config8(dev, 0xac, 0x06);
  38         pci_write_config8(dev, 0xad, 0x08);
  39         pci_write_config8(dev, 0xfd, 0x02);
  40         pci_write_config8(dev, 0x85, 0xb0);
  41         pci_write_config8(dev, 0x87, 0x07);
  42         pci_write_config8(dev, 0xfd, 0x06); // this is required for the following write to work
  43         pci_write_config8(dev, 0xaf, 0x88);
  44         pci_write_config8(dev, 0xfd, 0x04); // select AGP 3.0
  45         agp3 = pci_read_config8(dev, 0x84) & 0x08;
  46         pci_write_config8(dev, 0xb1, agp3 ? 0x00 : 0x9B);
  47         pci_write_config8(dev, 0xb3, agp3 ? 0x00 : 0x9B);
  48         pci_write_config8(dev, 0xb0, 0x40);
  49         pci_write_config8(dev, 0xb2, 0x11);
  50         pci_write_config8(dev, 0xed, 0x40);
  51 }
  52
  53 static void host_old_init(struct device *dev)
  54 {
  55         k8x8xx_vt8237r_cfg(dev, NULL);
  56 }
  57
  58 static void host_enable(struct device *dev)
  59 {
  60         /* Multiple function control */
  61         pci_write_config8(dev, K8T890_MULTIPLE_FN_EN, 0x01);
  62
  63         print_debug(" VIA_X_0 device dump:\n");
  64         dump_south(dev);
  65 }
  66
  67
  68 static void host_init(struct device *dev)
  69 {
  70         u8 reg;
  71
  72         /* AGP Capability Header Control */
  73         reg = pci_read_config8(dev, 0x4d);
  74         reg |= 0x20; /* GART access enabled by either D0F0 Rx90[8] or D1F0 Rx90[8] */
  75         pci_write_config8(dev, 0x4d, reg);
  76
  77         /* GD Output Stagger Delay */
  78         reg = pci_read_config8(dev, 0x42);
  79         reg |= 0x10; /* AD[31:16] with 1ns */
  80         pci_write_config8(dev, 0x42, reg);
  81
  82         /* AGP Control */
  83         reg = pci_read_config8(dev, 0xbc);
  84         reg |= 0x20; /* AGP Read Snoop DRAM Post-Write Buffer */
  85         pci_write_config8(dev, 0xbc, reg);
  86
  87 }
  88
  89 static const struct device_operations host_ops_old = {
  90         .read_resources         = pci_dev_read_resources,
  91         .set_resources          = pci_dev_set_resources,
  92         .enable_resources       = pci_dev_enable_resources,
  93         .enable                 = host_old_enable,
  94         .init                   = host_old_init,
  95         .ops_pci                = 0,
  96 };
  97
  98 static const struct device_operations host_ops_t = {
  99         .read_resources         = pci_dev_read_resources,
 100         .set_resources          = pci_dev_set_resources,
 101         .enable_resources       = pci_dev_enable_resources,
 102         .enable                 = host_enable,
 103         .ops_pci                = 0,
 104 };
 105
 106 static const struct device_operations host_ops_m = {
 107         .read_resources         = pci_dev_read_resources,
 108         .set_resources          = pci_dev_set_resources,
 109         .enable_resources       = pci_dev_enable_resources,
 110         .enable                 = host_enable,
 111         .init                   = host_init,
 112         .ops_pci                = 0,
 113 };
 114
 115 static const struct pci_driver northbridge_driver_t800_old __pci_driver = {
 116         .ops    = &host_ops_old,
 117         .vendor = PCI_VENDOR_ID_VIA,
 118         .device = PCI_DEVICE_ID_VIA_K8T800_AGP,
 119 };
 120
 121 static const struct pci_driver northbridge_driver_t800 __pci_driver = {
 122         .ops    = &host_ops_t,
 123         .vendor = PCI_VENDOR_ID_VIA,
 124         .device = PCI_DEVICE_ID_VIA_K8T800_HT_AGP_CTR,
 125 };
 126
 127 static const struct pci_driver northbridge_driver_m800 __pci_driver = {
 128         .ops    = &host_ops_m,
 129         .vendor = PCI_VENDOR_ID_VIA,
 130         .device = PCI_DEVICE_ID_VIA_K8M800_HT_AGP_CTR,
 131 };
 132
 133 static const struct pci_driver northbridge_driver_t890 __pci_driver = {
 134         .ops    = &host_ops_t,
 135         .vendor = PCI_VENDOR_ID_VIA,
 136         .device = PCI_DEVICE_ID_VIA_K8T890CE_0,
 137 };
 138
 139 static const struct pci_driver northbridge_driver_t890cf __pci_driver = {
 140         .ops    = &host_ops_t,
 141         .vendor = PCI_VENDOR_ID_VIA,
 142         .device = PCI_DEVICE_ID_VIA_K8T890CF_0,
 143 };
 144
 145 static const struct pci_driver northbridge_driver_m890 __pci_driver = {
 146         .ops    = &host_ops_m,
 147         .vendor = PCI_VENDOR_ID_VIA,
 148         .device = PCI_DEVICE_ID_VIA_K8M890CE_0,
 149 };