2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <device/device.h>
21 #include <device/pci.h>
22 #include <device/pci_ids.h>
23 #include <console/console.h>
24 #include <cpu/x86/msr.h>
25 #include <cpu/amd/mtrr.h>
26 #include <pc80/mc146818rtc.h>
30 static void dram_enable(struct device *dev)
36 * Enable Lowest Interrupt arbitration for APIC, enable NB APIC
37 * decoding, MSI support, no SMRAM, compatible SMM.
39 pci_write_config8(dev, 0x86, 0x39);
42 * We want to use the 0xC0000-0xEFFFF as RAM mark area as RW, even if
43 * memory is doing K8 the DMA from SB will fail if we have it wrong,
44 * AND even we have it here, we must later copy it to SB to make it work :/
47 /* For CC000-CFFFF, bits 7:6 (10 = REn, 01 = WEn) bits 1:0 for
50 pci_write_config8(dev, 0x80, 0xff);
51 /* For page D0000-DFFFF */
52 pci_write_config8(dev, 0x81, 0xff);
53 /* For page E0000-EFFFF */
54 pci_write_config8(dev, 0x82, 0xff);
55 pci_write_config8(dev, 0x83, 0x30);
58 reg = pci_read_config16(dev, 0x84);
60 pci_write_config16(dev, 0x84, (msr.lo >> 16) | reg);
62 reg = pci_read_config16(dev, 0x88);
65 /* The Address Next to the Last Valid DRAM Address */
66 pci_write_config16(dev, 0x88, (msr.lo >> 24) | reg);
71 extern uint64_t uma_memory_base, uma_memory_size;
74 static void dram_enable_k8m890(struct device *dev)
82 if (CONFIG_VIDEO_MB == -1) {
83 ret = get_option(&fbbits, "videoram_size");
85 printk(BIOS_WARNING, "Failed to get videoram size (error %d), using default.\n", ret);
89 if ((fbbits < 1) || (fbbits > 7)) {
90 printk(BIOS_WARNING, "Invalid videoram size (%d), using default.\n",
94 uma_memory_size = 4 << (fbbits + 20);
96 uma_memory_size = (CONFIG_VIDEO_MB << 20);
100 uma_memory_base = msr.lo - uma_memory_size;
101 printk(BIOS_INFO, "K8M890: UMA base is %llx size is %u (MB)\n", uma_memory_base,
102 (u32) (uma_memory_size / 1024 / 1024));
103 /* enable VGA, so the bridges gets VGA_EN and resources are set */
104 pci_write_config8(dev, 0xa1, 0x80);
110 k8m890_host_fb_size_get(void)
112 struct device *dev = dev_find_device(PCI_VENDOR_ID_VIA,
113 PCI_DEVICE_ID_VIA_K8M890CE_3, 0);
116 tmp = pci_read_config8(dev, 0xA1);
119 return 4 << (tmp & 7);
124 static void dram_init_fb(struct device *dev)
128 * Enable the internal GFX bit 7 of reg 0xa1 plus in same reg:
129 * bits 6:4 X fbuffer size will be 2^(X+2) or 100 = 64MB, 101 = 128MB
130 * bits 3:0 BASE [31:28]
131 * reg 0xa0 bits 7:1 BASE [27:21] bit0 enable CPU access
133 unsigned int fbbits = 0;
136 fbbits = ((log2(uma_memory_size >> 20) - 2) << 4);
137 printk(BIOS_INFO, "K8M890: Using a %dMB framebuffer.\n", (unsigned int) (uma_memory_size >> 20));
139 /* Step 1: enable UMA but no FB */
140 pci_write_config8(dev, 0xa1, 0x80);
142 /* Step 2: enough is just the FB size, the CPU accessible address is not needed */
144 pci_write_config8(dev, 0xa1, tmp);
146 /* TODO K8 needs some UMA fine tuning too maybe call some generic routine here? */
150 static const struct device_operations dram_ops_t = {
151 .read_resources = pci_dev_read_resources,
152 .set_resources = pci_dev_set_resources,
153 .enable_resources = pci_dev_enable_resources,
154 .enable = dram_enable,
158 static const struct device_operations dram_ops_m = {
159 .read_resources = pci_dev_read_resources,
160 .set_resources = pci_dev_set_resources,
161 .enable_resources = pci_dev_enable_resources,
162 .enable = dram_enable_k8m890,
163 .init = dram_init_fb,
167 static const struct pci_driver northbridge_driver_t __pci_driver = {
169 .vendor = PCI_VENDOR_ID_VIA,
170 .device = PCI_DEVICE_ID_VIA_K8T890CE_3,
173 static const struct pci_driver northbridge_driver_tcf __pci_driver = {
175 .vendor = PCI_VENDOR_ID_VIA,
176 .device = PCI_DEVICE_ID_VIA_K8T890CF_3,
179 static const struct pci_driver northbridge_driver_m __pci_driver = {
181 .vendor = PCI_VENDOR_ID_VIA,
182 .device = PCI_DEVICE_ID_VIA_K8M890CE_3,