src/southbridge/via/k8t890/ctrl.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
   5  * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me@gmail.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  19  */
  20
  21 #include <device/device.h>
  22 #include <device/pci.h>
  23 #include <device/pci_ops.h>
  24 #include <device/pci_ids.h>
  25 #include <console/console.h>
  26 #include "k8x8xx.h"
  27
  28 /* We support here K8M890/K8T890 and VT8237R PCI1/Vlink which setup is not in separate
  29  * PCI device 0:11.7, but it is mapped to PCI 0:0.7 (0x70-0x7c for PCI1)
  30  */
  31
  32 static void vt8237r_cfg(struct device *dev, struct device *devsb)
  33 {
  34         u8 regm3;
  35         struct k8x8xx_vt8237_mirrored_regs mregs;
  36
  37         pci_write_config8(dev, 0x70, 0xc2);
  38
  39         /* PCI Control */
  40         pci_write_config8(dev, 0x72, 0xee);
  41         pci_write_config8(dev, 0x73, 0x01);
  42         pci_write_config8(dev, 0x74, 0x24);
  43         pci_write_config8(dev, 0x75, 0x0f);
  44         pci_write_config8(dev, 0x76, 0x50);
  45         pci_write_config8(dev, 0x77, 0x08);
  46         pci_write_config8(dev, 0x78, 0x01);
  47         /* APIC on HT */
  48         pci_write_config8(dev, 0x7c, 0x7f);
  49         pci_write_config8(dev, 0x7f, 0x02);
  50
  51         k8x8xx_vt8237_mirrored_regs_fill(&mregs);
  52
  53         pci_write_config8(dev, 0x57, mregs.shadow_mem_ctrl);            /* Shadow mem CTRL */
  54         pci_write_config8(dev, 0x61, mregs.rom_shadow_ctrl_pg_c);       /* Shadow page C */
  55         pci_write_config8(dev, 0x62, mregs.rom_shadow_ctrl_pg_d);       /* Shadow page D */
  56         pci_write_config8(dev, 0xe6, mregs.smm_apic_decoding);          /* SMM and APIC decoding */
  57
  58         regm3 = mregs.rom_shadow_ctrl_pg_e_memhole_smi_decoding;        /* Shadow page E */
  59
  60         /*
  61          * All access bits for 0xE0000-0xEFFFF encode as just 2 bits!
  62          * So the NB reg is quite inconsistent, we expect there only 0xff or 0x00,
  63          * and write them to 0x63 7-6 but! VIA 8237A has the mirror at 0x64!
  64          */
  65         if (regm3 == 0xff)
  66                 regm3 = 0xc0;
  67         else
  68                 regm3 = 0x0;
  69
  70         /* Shadow page F + memhole copy */
  71         pci_write_config8(dev, 0x63, regm3 | (mregs.rom_shadow_ctrl_pg_f_memhole & 0x3F));
  72
  73 }
  74
  75
  76
  77 /**
  78  * Setup the V-Link for VT8237R, 8X mode.
  79  *
  80  * For K8T890CF VIA recommends what is in VIA column, AW is award 8X:
  81  *
  82  *                                               REG   DEF   AW  VIA-8X VIA-4X
  83  *                                               -----------------------------
  84  * NB V-Link Manual Driving Control strobe       0xb5  0x46  0x46  0x88  0x88
  85  * NB V-Link Manual Driving Control - Data       0xb6  0x46  0x46  0x88  0x88
  86  * NB V-Link Receiving Strobe Delay              0xb7  0x02  0x02  0x61  0x01
  87  * NB V-Link Compensation Control bit4,0 (b5,b6) 0xb4  0x10  0x10  0x11  0x11
  88  * SB V-Link Strobe Drive Control                0xb9  0x00  0xa5  0x98  0x98
  89  * SB V-Link Data drive Control????              0xba  0x00  0xbb  0x77  0x77
  90  * SB V-Link Receive Strobe Delay????            0xbb  0x04  0x11  0x11  0x11
  91  * SB V-Link Compensation Control bit0 (use b9)  0xb8  0x00  0x01  0x01  0x01
  92  * V-Link CKG Control                            0xb0  0x05  0x05  0x06  0x03
  93  * V-Link CKG Control                            0xb1  0x05  0x05  0x01  0x03
  94  */
  95
  96 static void vt8237r_vlink_init(struct device *dev)
  97 {
  98         u8 reg;
  99
 100         /*
 101          * This init code is valid only for the VT8237R! For different
 102          * sounthbridges (e.g. VT8237A, VT8237S, VT8237 (without plus R)
 103          * and VT8251) a different init code is required.
 104          */
 105
 106         pci_write_config8(dev, 0xb5, 0x88);
 107         pci_write_config8(dev, 0xb6, 0x88);
 108         pci_write_config8(dev, 0xb7, 0x61);
 109
 110         reg = pci_read_config8(dev, 0xb4);
 111         reg |= 0x11;
 112         pci_write_config8(dev, 0xb4, reg);
 113
 114         pci_write_config8(dev, 0xb9, 0x98);
 115         pci_write_config8(dev, 0xba, 0x77);
 116         pci_write_config8(dev, 0xbb, 0x11);
 117
 118         reg = pci_read_config8(dev, 0xb8);
 119         reg |= 0x1;
 120         pci_write_config8(dev, 0xb8, reg);
 121
 122         pci_write_config8(dev, 0xb0, 0x06);
 123         pci_write_config8(dev, 0xb1, 0x01);
 124
 125         /* Program V-link 8X 16bit full duplex, parity enabled. */
 126         pci_write_config8(dev, 0x48, 0xa3);
 127 }
 128
 129 static void ctrl_init(struct device *dev)
 130 {
 131
 132         print_debug("K8x8xx: Initializing V-Link to VT8237R sb: ");
 133         /* TODO: Fix some ordering issue fo V-link set Rx77[6] and PCI1_Rx4F[0]
 134            should to 1 */
 135
 136         /* C2P Read ACK Return Priority */
 137         /* PCI CFG Address bits[27:24] are used as extended register address
 138            bit[11:8] */
 139
 140         pci_write_config8(dev, 0x47, 0x30);
 141
 142         /* VT8237R specific configuration  other SB are done in their own directories */
 143
 144         device_t devsb = dev_find_device(PCI_VENDOR_ID_VIA,
 145                                          PCI_DEVICE_ID_VIA_VT8237R_LPC, 0);
 146         if (devsb) {
 147                 vt8237r_vlink_init(dev);
 148                 vt8237r_cfg(dev, devsb);
 149         } else {
 150                 print_debug("VT8237R LPC not found !\n");
 151                 return;
 152         }
 153         print_debug(" Done\n");
 154         print_debug(" VIA_X_7 device dump:\n");
 155         dump_south(dev);
 156
 157 }
 158
 159 static const struct device_operations ctrl_ops = {
 160         .read_resources         = pci_dev_read_resources,
 161         .set_resources          = pci_dev_set_resources,
 162         .enable_resources       = pci_dev_enable_resources,
 163         .init                   = ctrl_init,
 164         .ops_pci                = 0,
 165 };
 166
 167 static const struct pci_driver northbridge_driver_t800 __pci_driver = {
 168         .ops    = &ctrl_ops,
 169         .vendor = PCI_VENDOR_ID_VIA,
 170         .device = PCI_DEVICE_ID_VIA_K8T800_NB_SB_CTR,
 171 };
 172
 173 static const struct pci_driver northbridge_driver_m800 __pci_driver = {
 174         .ops    = &ctrl_ops,
 175         .vendor = PCI_VENDOR_ID_VIA,
 176         .device = PCI_DEVICE_ID_VIA_K8M800_NB_SB_CTR,
 177 };
 178
 179 static const struct pci_driver northbridge_driver_t890 __pci_driver = {
 180         .ops    = &ctrl_ops,
 181         .vendor = PCI_VENDOR_ID_VIA,
 182         .device = PCI_DEVICE_ID_VIA_K8T890CE_7,
 183 };
 184
 185 static const struct pci_driver northbridge_driver_t890cf __pci_driver = {
 186         .ops    = &ctrl_ops,
 187         .vendor = PCI_VENDOR_ID_VIA,
 188         .device = PCI_DEVICE_ID_VIA_K8T890CF_7,
 189 };
 190
 191 static const struct pci_driver northbridge_driver_m890 __pci_driver = {
 192         .ops    = &ctrl_ops,
 193         .vendor = PCI_VENDOR_ID_VIA,
 194         .device = PCI_DEVICE_ID_VIA_K8M890CE_7,
 195 };