2 * This file is part of the coreboot project.
4 * Copyright (C) 2010 Marc Bertens <mbertens@xs4all.nl>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <device/device.h>
22 #include <device/pci.h>
23 #include <device/pci_ids.h>
24 #include <device/pci_ops.h>
25 #include <device/cardbus.h>
26 #include <console/console.h>
30 static void ti_pci1x2y_init(struct device *dev)
33 printk(BIOS_INFO, "Init of Texas Instruments PCI1x2x PCMCIA/CardBus controller\n");
34 struct southbridge_ti_pci1x2x_config *conf = dev->chip_info;
37 /* Cache Line Size (offset 0x0C) */
38 pci_write_config8(dev, 0x0C, conf->clsr);
39 /* CardBus latency timer (offset 0x1B) */
40 pci_write_config8(dev, 0x1B, conf->cltr);
41 /* Bridge control (offset 0x3E) */
42 pci_write_config16(dev, 0x3E, conf->bcr);
43 /* System control (offset 0x80) */
44 pci_write_config32(dev, 0x80, conf->scr);
45 /* Multifunction routing */
46 pci_write_config32(dev, 0x8C, conf->mrr);
48 /* Set the device control register (0x92) accordingly. */
49 pci_write_config8(dev, 0x92, pci_read_config8(dev, 0x92) | 0x02);
52 static void ti_pci1x2y_set_subsystem(device_t dev, unsigned vendor, unsigned device)
55 * Enable change sub-vendor ID. Clear the bit 5 to enable to write
56 * to the sub-vendor/device ids at 40 and 42.
58 pci_write_config32(dev, 0x80, pci_read_config32(dev, 0x080) & ~0x10);
59 pci_write_config16(dev, 0x40, vendor);
60 pci_write_config16(dev, 0x42, device);
61 pci_write_config32(dev, 0x80, pci_read_config32(dev, 0x80) | 0x10);
64 static struct pci_operations ti_pci1x2y_pci_ops = {
65 .set_subsystem = ti_pci1x2y_set_subsystem,
68 struct device_operations southbridge_ti_pci1x2x_pciops = {
69 .read_resources = cardbus_read_resources,
70 .set_resources = pci_dev_set_resources,
71 .enable_resources = cardbus_enable_resources,
72 .init = ti_pci1x2y_init,
74 .ops_pci = &ti_pci1x2y_pci_ops,
77 static const struct pci_driver ti_pci1225_driver __pci_driver = {
78 .ops = &southbridge_ti_pci1x2x_pciops,
79 .vendor = PCI_VENDOR_ID_TI,
80 .device = PCI_DEVICE_ID_TI_1225,
83 static const struct pci_driver ti_pci1420_driver __pci_driver = {
84 .ops = &southbridge_ti_pci1x2x_pciops,
85 .vendor = PCI_VENDOR_ID_TI,
86 .device = PCI_DEVICE_ID_TI_1420,
89 static const struct pci_driver ti_pci1510_driver __pci_driver = {
90 .ops = &southbridge_ti_pci1x2x_pciops,
91 .vendor = PCI_VENDOR_ID_TI,
92 .device = PCI_DEVICE_ID_TI_1510,
95 static const struct pci_driver ti_pci1520_driver __pci_driver = {
96 .ops = &southbridge_ti_pci1x2x_pciops,
97 .vendor = PCI_VENDOR_ID_TI,
98 .device = PCI_DEVICE_ID_TI_1520,
101 struct chip_operations southbridge_ti_pci1x2x_ops = {
102 CHIP_NAME("TI PCI1x2x Cardbus controller")