2 * This file is part of the coreboot project.
4 * Copyright (C) 2010 Marc Bertens <mbertens@xs4all.nl>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <device/device.h>
21 #include <device/pci.h>
22 #include <device/pci_ids.h>
23 #include <device/pci_ops.h>
24 #include <console/console.h>
26 #if ( !defined( CONFIG_TI_PCMCIA_CARDBUS_CMDR ) || \
27 !defined( CONFIG_TI_PCMCIA_CARDBUS_CLSR ) || \
28 !defined( CONFIG_TI_PCMCIA_CARDBUS_CLTR ) || \
29 !defined( CONFIG_TI_PCMCIA_CARDBUS_BCR ) || \
30 !defined( CONFIG_TI_PCMCIA_CARDBUS_SCR ) || \
31 !defined( CONFIG_TI_PCMCIA_CARDBUS_MRR ) )
32 #error "you must supply these values in your mainboard-specific Kconfig file"
35 static void ti_pci1x2y_init(struct device *dev)
37 printk(BIOS_INFO, "Init of Texas Instruments PCI1x2x PCMCIA/CardBus controller\n");
38 // Command register (offset 04)
39 pci_write_config16( dev, 0x04, CONFIG_TI_PCMCIA_CARDBUS_CMDR );
40 // Cache Line Size Register (offset 0x0C)
41 pci_write_config8( dev, 0x0C, CONFIG_TI_PCMCIA_CARDBUS_CLSR );
42 // CardBus latency timer register (offset 1B)
43 pci_write_config8( dev, 0x1B, CONFIG_TI_PCMCIA_CARDBUS_CLTR );
44 // Bridge control register (offset 3E)
45 pci_write_config16( dev, 0x3E, CONFIG_TI_PCMCIA_CARDBUS_BCR );
46 /** Enable change sub-vendor id
47 * Clear the bit 5 to enable to write to the sub-vendor/device ids at 40 and 42 */
48 pci_write_config32( dev, 0x80, 0x10 );
49 pci_write_config32( dev, 0x40, PCI_VENDOR_ID_NOKIA );
50 // Now write the correct value for SCR
51 // System Control Register (offset 0x80)
52 pci_write_config32( dev, 0x80, CONFIG_TI_PCMCIA_CARDBUS_SCR );
53 // Multifunction routing register
54 pci_write_config32( dev, 0x8C, CONFIG_TI_PCMCIA_CARDBUS_MRR );
55 // Set Device Control Register (0x92) accordingly
56 pci_write_config8( dev, 0x92, pci_read_config8( dev, 0x92 ) | 0x02 );
60 static struct device_operations ti_pci1x2y_ops = {
61 .read_resources = NULL, //pci_dev_read_resources,
62 .set_resources = pci_dev_set_resources,
63 .enable_resources = pci_dev_enable_resources,
64 .init = ti_pci1x2y_init,
68 static const struct pci_driver ti_pci1225_driver __pci_driver = {
69 .ops = &ti_pci1x2y_ops,
70 .vendor = PCI_VENDOR_ID_TI,
71 .device = PCI_DEVICE_ID_TI_1225,
74 static const struct pci_driver ti_pci1420_driver __pci_driver = {
75 .ops = &ti_pci1x2y_ops,
76 .vendor = PCI_VENDOR_ID_TI,
77 .device = PCI_DEVICE_ID_TI_1420,
80 static const struct pci_driver ti_pci1520_driver __pci_driver = {
81 .ops = &ti_pci1x2y_ops,
82 .vendor = PCI_VENDOR_ID_TI,
83 .device = PCI_DEVICE_ID_TI_1420,