2 * This file is part of the coreboot project.
4 * Copyright (C) 2010 Marc Bertens <mbertens@xs4all.nl>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <device/device.h>
22 #include <device/pci.h>
23 #include <device/pci_ids.h>
24 #include <device/pci_ops.h>
25 #include <console/console.h>
29 static void ti_pci1x2y_init(struct device *dev)
32 printk(BIOS_INFO, "Init of Texas Instruments PCI1x2x PCMCIA/CardBus controller\n");
33 struct southbridge_ti_pci1x2x_config *conf = dev->chip_info;
36 /* Cache Line Size (offset 0x0C) */
37 pci_write_config8(dev, 0x0C, conf->clsr);
38 /* CardBus latency timer (offset 0x1B) */
39 pci_write_config8(dev, 0x1B, conf->cltr);
40 /* Bridge control (offset 0x3E) */
41 pci_write_config16(dev, 0x3E, conf->bcr);
42 /* System control (offset 0x80) */
43 pci_write_config32(dev, 0x80, conf->scr);
44 /* Multifunction routing */
45 pci_write_config32(dev, 0x8C, conf->mrr);
47 /* Set the device control register (0x92) accordingly. */
48 pci_write_config8(dev, 0x92, pci_read_config8(dev, 0x92) | 0x02);
51 static void ti_pci1x2y_set_subsystem(device_t dev, unsigned vendor, unsigned device)
54 * Enable change sub-vendor ID. Clear the bit 5 to enable to write
55 * to the sub-vendor/device ids at 40 and 42.
57 pci_write_config32(dev, 0x80, pci_read_config32(dev, 0x080) & ~0x10);
58 pci_write_config16(dev, 0x40, vendor);
59 pci_write_config16(dev, 0x42, device);
60 pci_write_config32(dev, 0x80, pci_read_config32(dev, 0x80) | 0x10);
63 static struct pci_operations ti_pci1x2y_pci_ops = {
64 .set_subsystem = ti_pci1x2y_set_subsystem,
67 struct device_operations southbridge_ti_pci1x2x_pciops = {
68 .read_resources = NULL, //pci_dev_read_resources,
69 .set_resources = pci_dev_set_resources,
70 .enable_resources = pci_dev_enable_resources,
71 .init = ti_pci1x2y_init,
73 .ops_pci = &ti_pci1x2y_pci_ops,
76 static const struct pci_driver ti_pci1225_driver __pci_driver = {
77 .ops = &southbridge_ti_pci1x2x_pciops,
78 .vendor = PCI_VENDOR_ID_TI,
79 .device = PCI_DEVICE_ID_TI_1225,
82 static const struct pci_driver ti_pci1420_driver __pci_driver = {
83 .ops = &southbridge_ti_pci1x2x_pciops,
84 .vendor = PCI_VENDOR_ID_TI,
85 .device = PCI_DEVICE_ID_TI_1420,
88 static const struct pci_driver ti_pci1510_driver __pci_driver = {
89 .ops = &southbridge_ti_pci1x2x_pciops,
90 .vendor = PCI_VENDOR_ID_TI,
91 .device = PCI_DEVICE_ID_TI_1510,
94 static const struct pci_driver ti_pci1520_driver __pci_driver = {
95 .ops = &southbridge_ti_pci1x2x_pciops,
96 .vendor = PCI_VENDOR_ID_TI,
97 .device = PCI_DEVICE_ID_TI_1520,
100 struct chip_operations southbridge_ti_pci1x2x_ops = {
101 CHIP_NAME("TI PCI1x2x Cardbus controller")