2 * This file is part of the LinuxBIOS project.
4 * Copyright (C) 2004 Tyan Computer
5 * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
6 * Copyright (C) 2006,2007 AMD
7 * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
8 * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
9 * Written by Morgan Tsai <my_tsai@sis.com> for SiS.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
26 #include <device/smbus_def.h>
28 #define SMBHSTSTAT 0x1
29 #define SMBHSTPRTCL 0x0
31 #define SMBXMITADD 0x2
32 #define SMBHSTDAT0 0x4
33 #define SMBHSTDAT1 0x5
35 /* Between 1-10 seconds, We should never timeout normally
36 * Longer than this is just painful when a timeout condition occurs.
38 #define SMBUS_TIMEOUT (100*1000*10)
40 static inline void smbus_delay(void)
45 static int smbus_wait_until_ready(unsigned smbus_io_base)
48 loops = SMBUS_TIMEOUT;
52 val = inb(smbus_io_base + SMBHSTSTAT);
57 outb(val,smbus_io_base + SMBHSTSTAT);
62 static int smbus_wait_until_done(unsigned smbus_io_base)
65 loops = SMBUS_TIMEOUT;
70 val = inb(smbus_io_base + 0x00);
71 if ( (val & 0xff) != 0x02) {
77 static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device)
79 unsigned char global_status_register;
82 /* set the device I'm talking too */
83 outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBXMITADD);
87 outb(0x05, smbus_io_base + SMBHSTPRTCL);
90 /* poll for transaction completion */
91 if (smbus_wait_until_done(smbus_io_base) < 0) {
95 global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */
97 /* read results of transaction */
98 byte = inb(smbus_io_base + SMBHSTCMD);
100 if (global_status_register != 0x80) { // lose check, otherwise it should be 0
105 static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned char val)
107 unsigned global_status_register;
109 outb(val, smbus_io_base + SMBHSTDAT0);
112 /* set the command... */
113 outb(val, smbus_io_base + SMBHSTCMD);
116 /* set the device I'm talking too */
117 outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBXMITADD);
120 /* set up for a byte data write */
121 outb(0x04, smbus_io_base + SMBHSTPRTCL);
124 /* poll for transaction completion */
125 if (smbus_wait_until_done(smbus_io_base) < 0) {
128 global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */;
130 if (global_status_register != 0x80) {
135 static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address)
137 unsigned char global_status_register;
140 outb(0xff, smbus_io_base + 0x00);
142 outb(0x20, smbus_io_base + 0x03);
145 outb(((device & 0x7f) << 1)|1 , smbus_io_base + 0x04);
147 outb(address & 0xff, smbus_io_base + 0x05);
149 outb(0x12, smbus_io_base + 0x03);
153 for(i=0;i<0x1000;i++)
155 if (inb(smbus_io_base + 0x00) != 0x08)
157 for(j=0;j<0xFFFF;j++);
161 global_status_register = inb(smbus_io_base + 0x00);
162 byte = inb(smbus_io_base + 0x08);
164 if (global_status_register != 0x08) { // lose check, otherwise it should be 0
165 print_debug("Fail");print_debug("\r\t");
168 print_debug("Success");print_debug("\r\t");
173 static int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, unsigned address, unsigned char val)
175 unsigned global_status_register;
177 outb(val, smbus_io_base + SMBHSTDAT0);
180 /* set the device I'm talking too */
181 outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBXMITADD);
184 outb(address & 0xff, smbus_io_base + SMBHSTCMD);
187 /* set up for a byte data write */
188 outb(0x06, smbus_io_base + SMBHSTPRTCL);
191 /* poll for transaction completion */
192 if (smbus_wait_until_done(smbus_io_base) < 0) {
195 global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */;
197 if (global_status_register != 0x80) {