2 * This file is part of the coreboot project.
4 * Copyright (C) 2004 Tyan Computer
5 * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
6 * Copyright (C) 2006,2007 AMD
7 * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
26 #define PCI_DEV(BUS, DEV, FN) ( \
27 (((BUS) & 0xFFF) << 20) | \
28 (((DEV) & 0x1F) << 15) | \
31 typedef unsigned device_t;
33 static void pci_write_config32(device_t dev, unsigned where, unsigned value)
36 addr = (dev>>4) | where;
37 outl(0x80000000 | (addr & ~3), 0xCF8);
41 static unsigned pci_read_config32(device_t dev, unsigned where)
44 addr = (dev>>4) | where;
45 outl(0x80000000 | (addr & ~3), 0xCF8);
49 #include "../../../northbridge/amd/amdk8/reset_test.c"
54 /* Try rebooting through port 0xcf9 */
55 /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */
56 outb((0 <<3)|(0<<2)|(1<<1), 0xcf9);
57 outb((0 <<3)|(1<<2)|(1<<1), 0xcf9);