src/southbridge/sis/sis966/sis966_nic.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2004 Tyan Computer
   5  * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
   6  * Copyright (C) 2006,2007 AMD
   7  * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
   8  * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
   9  * Written by Morgan Tsai <my_tsai@sis.com> for SiS.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  24  */
  25
  26 #include <console/console.h>
  27 #include <device/device.h>
  28 #include <device/smbus.h>
  29 #include <device/pci.h>
  30 #include <device/pci_ids.h>
  31 #include <device/pci_ops.h>
  32 #include <arch/io.h>
  33 #include <delay.h>
  34 #include "sis966.h"
  35
  36
  37 u8      SiS_SiS191_init[6][3]={
  38 {0x04, 0xFF, 0x07},
  39 {0x2C, 0xFF, 0x39},
  40 {0x2D, 0xFF, 0x10},
  41 {0x2E, 0xFF, 0x91},
  42 {0x2F, 0xFF, 0x01},
  43 {0x00, 0x00, 0x00}                                      //End of table
  44 };
  45
  46
  47 #define StatusReg       0x1
  48 #define SMI_READ        0x0
  49 #define SMI_REQUEST     0x10
  50 #define TRUE            1
  51 #define FALSE           0
  52
  53 u16 MacAddr[3];
  54
  55
  56 static void writeApcByte(int addr, u8 value)
  57 {
  58     outb(addr,0x78);
  59     outb(value,0x79);
  60 }
  61
  62 static u8 readApcByte(int addr)
  63 {
  64     u8 value;
  65     outb(addr,0x78);
  66     value=inb(0x79);
  67     return(value);
  68 }
  69
  70 static void readApcMacAddr(void)
  71 {
  72     u8 i;
  73
  74 // enable APC in south bridge sis966 D2F0
  75
  76     outl(0x80001048,0xcf8);
  77     outl((inl(0xcfc) & 0xfffffffd),0xcfc ); // enable IO78/79h for APC Index/Data
  78
  79     printk(BIOS_DEBUG, "MAC addr in APC = ");
  80     for(i = 0x9 ; i <=0xe ; i++)
  81     {
  82         printk(BIOS_DEBUG, "%2.2x",readApcByte(i));
  83     }
  84     printk(BIOS_DEBUG, "\n");
  85
  86     /* Set APC Reload */
  87     writeApcByte(0x7,readApcByte(0x7)&0xf7);
  88     writeApcByte(0x7,readApcByte(0x7)|0x0a);
  89
  90     /* disable APC in south bridge */
  91     outl(0x80001048,0xcf8);
  92     outl(inl(0xcfc)&0xffffffbf,0xcfc);
  93 }
  94
  95 static void set_apc(struct device *dev)
  96 {
  97     u16 addr;
  98     u16 i;
  99     u8   bTmp;
 100
 101     /* enable APC in south bridge sis966 D2F0 */
 102     outl(0x80001048,0xcf8);
 103     outl((inl(0xcfc) & 0xfffffffd),0xcfc ); // enable IO78/79h for APC Index/Data
 104
 105     for(i = 0 ; i <3; i++)
 106     {
 107        addr=0x9+2*i;
 108        writeApcByte(addr,(u8)(MacAddr[i]&0xFF));
 109         writeApcByte(addr+1L,(u8)((MacAddr[i]>>8)&0xFF));
 110         // printf("%x - ",readMacAddrByte(0x59+i));
 111     }
 112
 113     /* Set APC Reload */
 114     writeApcByte(0x7,readApcByte(0x7)&0xf7);
 115     writeApcByte(0x7,readApcByte(0x7)|0x0a);
 116
 117     /* disable APC in south bridge */
 118     outl(0x80001048,0xcf8);
 119     outl(inl(0xcfc)&0xffffffbf,0xcfc);
 120
 121     // CFG reg0x73 bit=1, tell driver MAC Address load to APC
 122     bTmp = pci_read_config8(dev, 0x73);
 123     bTmp|=0x1;
 124     pci_write_config8(dev, 0x73, bTmp);
 125 }
 126
 127 //-----------------------------------------------------------------------------
 128 // Procedure:   ReadEEprom
 129 //
 130 // Description: This routine serially reads one word out of the EEPROM.
 131 //
 132 // Arguments:
 133 //      Reg - EEPROM word to read.
 134 //
 135 // Returns:
 136 //      Contents of EEPROM word (Reg).
 137 //-----------------------------------------------------------------------------
 138 #define LoopNum 200
 139 static  unsigned long ReadEEprom( struct device *dev,  u32 base,  u32 Reg)
 140 {
 141     u32         data;
 142     u32         i;
 143     u32         ulValue;
 144
 145
 146     ulValue = (0x80 | (0x2 << 8) | (Reg << 10));  //BIT_7
 147
 148     write32(base+0x3c, ulValue);
 149
 150     mdelay(10);
 151
 152     for(i=0 ; i <= LoopNum; i++)
 153     {
 154         ulValue=read32(base+0x3c);
 155
 156         if(!(ulValue & 0x0080)) //BIT_7
 157             break;
 158
 159         mdelay(100);
 160     }
 161
 162     mdelay(50);
 163
 164     if(i==LoopNum)   data=0x10000;
 165     else{
 166         ulValue=read32(base+0x3c);
 167         data = ((ulValue & 0xffff0000) >> 16);
 168     }
 169
 170     return data;
 171 }
 172
 173 static int phy_read(u32  base, unsigned phy_addr, unsigned phy_reg)
 174 {
 175     u32   ulValue;
 176     u32   Read_Cmd;
 177     u16   usData;
 178
 179
 180
 181            Read_Cmd = ((phy_reg << 11) |
 182                        (phy_addr << 6) |
 183                        SMI_READ |
 184                        SMI_REQUEST);
 185
 186            // SmiMgtInterface Reg is the SMI management interface register(offset 44h) of MAC
 187           write32(base+0x44, Read_Cmd);
 188
 189            // Polling SMI_REQ bit to be deasserted indicated read command completed
 190            do
 191            {
 192                // Wait 20 usec before checking status
 193                    mdelay(20);
 194                ulValue = read32(base+0x44);
 195            } while((ulValue & SMI_REQUEST) != 0);
 196             //printk(BIOS_DEBUG, "base %x cmd %lx ret val %lx\n", tmp,Read_Cmd,ulValue);
 197            usData=(ulValue>>16);
 198
 199
 200
 201         return usData;
 202
 203 }
 204
 205 // Detect a valid PHY
 206 // If there exist a valid PHY then return TRUE, else return FALSE
 207 static int phy_detect(u32 base,u16 *PhyAddr) //BOOL PHY_Detect()
 208 {
 209     int               bFoundPhy = FALSE;
 210     u16         usData;
 211     int                PhyAddress = 0;
 212
 213
 214         // Scan all PHY address(0 ~ 31) to find a valid PHY
 215         for(PhyAddress = 0; PhyAddress < 32; PhyAddress++)
 216         {
 217                 usData=phy_read(base,PhyAddress,StatusReg);  // Status register is a PHY's register(offset 01h)
 218
 219            // Found a valid PHY
 220
 221            if((usData != 0x0) && (usData != 0xffff))
 222            {
 223                bFoundPhy = TRUE;
 224                break;
 225            }
 226         }
 227
 228
 229         if(!bFoundPhy)
 230         {
 231             printk(BIOS_DEBUG, "PHY not found !!!! \n");
 232         }
 233
 234        *PhyAddr=PhyAddress;
 235
 236         return bFoundPhy;
 237 }
 238
 239
 240 static void nic_init(struct device *dev)
 241 {
 242         int val;
 243         u16 PhyAddr;
 244         u32 base;
 245         struct resource *res;
 246
 247         print_debug("NIC_INIT:---------->\n");
 248
 249 //-------------- enable NIC (SiS19x) -------------------------
 250 {
 251         u8  temp8;
 252         int i=0;
 253         while(SiS_SiS191_init[i][0] != 0)
 254         {
 255                 temp8 = pci_read_config8(dev, SiS_SiS191_init[i][0]);
 256                 temp8 &= SiS_SiS191_init[i][1];
 257                 temp8 |= SiS_SiS191_init[i][2];
 258                 pci_write_config8(dev, SiS_SiS191_init[i][0], temp8);
 259                 i++;
 260         };
 261 }
 262 //-----------------------------------------------------------
 263
 264 {
 265         unsigned long  i;
 266         unsigned long ulValue;
 267
 268         res = find_resource(dev, 0x10);
 269
 270         if(!res)
 271         {
 272                 printk(BIOS_DEBUG, "NIC Cannot find resource..\n");
 273                 return;
 274         }
 275         base = res->base;
 276         printk(BIOS_DEBUG, "NIC base address %x\n",base);
 277
 278         if(!(val=phy_detect(base,&PhyAddr)))
 279         {
 280                printk(BIOS_DEBUG, "PHY detect fail !!!!\n");
 281                 return;
 282         }
 283
 284         ulValue=read32(base + 0x38L);   //  check EEPROM existing
 285
 286         if((ulValue & 0x0002))
 287         {
 288
 289           //    read MAC address from EEPROM at first
 290
 291           //    if that is valid we will use that
 292
 293                         printk(BIOS_DEBUG, "EEPROM contents %lx \n",ReadEEprom( dev,  base,  0LL));
 294                         for(i=0;i<3;i++) {
 295                                 //status = smbus_read_byte(dev_eeprom, i);
 296                                 ulValue=ReadEEprom( dev,  base,  i+3L);
 297                                 if (ulValue ==0x10000) break;  // error
 298
 299                                 MacAddr[i] =ulValue & 0xFFFF;
 300
 301                         }
 302         }else{
 303                  // read MAC address from firmware
 304                  printk(BIOS_DEBUG, "EEPROM invalid!!\nReg 0x38h=%.8lx \n",ulValue);
 305                  MacAddr[0]=read16(0xffffffc0); // mac address store at here
 306                  MacAddr[1]=read16(0xffffffc2);
 307                  MacAddr[2]=read16(0xffffffc4);
 308         }
 309
 310         set_apc(dev);
 311
 312         readApcMacAddr();
 313
 314 #if DEBUG_NIC
 315 {
 316         int i;
 317
 318         print_debug("****** NIC PCI config ******");
 319         print_debug("\n    03020100  07060504  0B0A0908  0F0E0D0C");
 320
 321         for(i=0;i<0xff;i+=4){
 322                 if((i%16)==0){
 323                         print_debug("\n");
 324                         print_debug_hex8(i);
 325                         print_debug(": ");
 326                 }
 327                 print_debug_hex32(pci_read_config32(dev,i));
 328                 print_debug("  ");
 329         }
 330         print_debug("\n");
 331 }
 332
 333
 334 #endif
 335
 336 }
 337
 338 print_debug("NIC_INIT:<----------\n");
 339 return;
 340
 341
 342 }
 343
 344 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 345 {
 346         pci_write_config32(dev, 0x40,
 347                 ((device & 0xffff) << 16) | (vendor & 0xffff));
 348 }
 349
 350 static struct pci_operations lops_pci = {
 351         .set_subsystem  = lpci_set_subsystem,
 352 };
 353
 354 static struct device_operations nic_ops  = {
 355         .read_resources = pci_dev_read_resources,
 356         .set_resources  = pci_dev_set_resources,
 357         .enable_resources       = pci_dev_enable_resources,
 358         .init           = nic_init,
 359         .scan_bus       = 0,
 360 //      .enable         = sis966_enable,
 361         .ops_pci        = &lops_pci,
 362 };
 363
 364 static const struct pci_driver nic_driver __pci_driver = {
 365         .ops    = &nic_ops,
 366         .vendor = PCI_VENDOR_ID_SIS,
 367         .device = PCI_DEVICE_ID_SIS_SIS966_NIC,
 368 };