src/southbridge/sis/sis966/sis966_nic.c

   1 /*
   2  * This file is part of the LinuxBIOS project.
   3  *
   4  * Copyright (C) 2004 Tyan Computer
   5  * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
   6  * Copyright (C) 2006,2007 AMD
   7  * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
   8  * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
   9  * Written by Morgan Tsai <my_tsai@sis.com> for SiS.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  24  */
  25
  26 #include <console/console.h>
  27 #include <device/device.h>
  28 #include <device/smbus.h>
  29 #include <device/pci.h>
  30 #include <device/pci_ids.h>
  31 #include <device/pci_ops.h>
  32 #include <arch/io.h>
  33 #include <delay.h>
  34 #include "sis966.h"
  35
  36
  37 uint8_t SiS_SiS191_init[6][3]={
  38 {0x04, 0xFF, 0x07},
  39 {0x2C, 0xFF, 0x39},
  40 {0x2D, 0xFF, 0x10},
  41 {0x2E, 0xFF, 0x91},
  42 {0x2F, 0xFF, 0x01},
  43 {0x00, 0x00, 0x00}                                      //End of table
  44 };
  45
  46
  47 #define StatusReg       0x1
  48 #define SMI_READ        0x0
  49 #define SMI_REQUEST     0x10
  50 #define TRUE            1
  51 #define FALSE           0
  52
  53 uint16_t MacAddr[3];
  54
  55
  56 void writeApcByte(int addr, uint8_t value)
  57 {
  58     outb(addr,0x78);
  59     outb(value,0x79);
  60 }
  61 uint8_t readApcByte(int addr)
  62 {
  63     uint8_t value;
  64     outb(addr,0x78);
  65     value=inb(0x79);
  66     return(value);
  67 }
  68
  69 static void readApcMacAddr(void)
  70 {
  71     uint8_t i;
  72
  73 // enable APC in south bridge sis966 D2F0
  74
  75     outl(0x80001048,0xcf8);
  76     outl((inl(0xcfc) & 0xfffffffd),0xcfc ); // enable IO78/79h for APC Index/Data
  77
  78     printk_debug("MAC addr in APC = ");
  79     for(i = 0x9 ; i <=0xe ; i++)
  80     {
  81         printk_debug("%2.2x",readApcByte(i));
  82     }
  83     printk_debug("\n");
  84
  85     /* Set APC Reload */
  86     writeApcByte(0x7,readApcByte(0x7)&0xf7);
  87     writeApcByte(0x7,readApcByte(0x7)|0x0a);
  88
  89     /* disable APC in south bridge */
  90     outl(0x80001048,0xcf8);
  91     outl(inl(0xcfc)&0xffffffbf,0xcfc);
  92 }
  93
  94 static void set_apc(struct device *dev)
  95 {
  96     uint16_t addr;
  97     uint16_t i;
  98     uint8_t   bTmp;
  99
 100     /* enable APC in south bridge sis966 D2F0 */
 101     outl(0x80001048,0xcf8);
 102     outl((inl(0xcfc) & 0xfffffffd),0xcfc ); // enable IO78/79h for APC Index/Data
 103
 104     for(i = 0 ; i <3; i++)
 105     {
 106        addr=0x9+2*i;
 107        writeApcByte(addr,(uint8_t)(MacAddr[i]&0xFF));
 108         writeApcByte(addr+1L,(uint8_t)((MacAddr[i]>>8)&0xFF));
 109         // printf("%x - ",readMacAddrByte(0x59+i));
 110     }
 111
 112     /* Set APC Reload */
 113     writeApcByte(0x7,readApcByte(0x7)&0xf7);
 114     writeApcByte(0x7,readApcByte(0x7)|0x0a);
 115
 116     /* disable APC in south bridge */
 117     outl(0x80001048,0xcf8);
 118     outl(inl(0xcfc)&0xffffffbf,0xcfc);
 119
 120     // CFG reg0x73 bit=1, tell driver MAC Address load to APC
 121     bTmp = pci_read_config8(dev, 0x73);
 122     bTmp|=0x1;
 123     pci_write_config8(dev, 0x73, bTmp);
 124 }
 125
 126 //-----------------------------------------------------------------------------
 127 // Procedure:   ReadEEprom
 128 //
 129 // Description: This routine serially reads one word out of the EEPROM.
 130 //
 131 // Arguments:
 132 //      Reg - EEPROM word to read.
 133 //
 134 // Returns:
 135 //      Contents of EEPROM word (Reg).
 136 //-----------------------------------------------------------------------------
 137 #define LoopNum 200
 138 static  unsigned long ReadEEprom( struct device *dev,  uint32_t base,  uint32_t Reg)
 139 {
 140     uint32_t    data;
 141     uint32_t    i;
 142     uint32_t    ulValue;
 143
 144
 145     ulValue = (0x80 | (0x2 << 8) | (Reg << 10));  //BIT_7
 146
 147     writel( ulValue,base+0x3c);
 148
 149     mdelay(10);
 150
 151     for(i=0 ; i <= LoopNum; i++)
 152     {
 153         ulValue=readl(base+0x3c);
 154
 155         if(!(ulValue & 0x0080)) //BIT_7
 156             break;
 157
 158         mdelay(100);
 159     }
 160
 161     mdelay(50);
 162
 163     if(i==LoopNum)   data=0x10000;
 164     else{
 165         ulValue=readl(base+0x3c);
 166         data = ((ulValue & 0xffff0000) >> 16);
 167     }
 168
 169     return data;
 170 }
 171
 172 static int phy_read(uint32_t  base, unsigned phy_addr, unsigned phy_reg)
 173 {
 174     uint32_t   ulValue;
 175     uint32_t   Read_Cmd;
 176     uint16_t   usData;
 177
 178
 179
 180            Read_Cmd = ((phy_reg << 11) |
 181                        (phy_addr << 6) |
 182                        SMI_READ |
 183                        SMI_REQUEST);
 184
 185            // SmiMgtInterface Reg is the SMI management interface register(offset 44h) of MAC
 186           writel( Read_Cmd,base+0x44);
 187
 188            // Polling SMI_REQ bit to be deasserted indicated read command completed
 189            do
 190            {
 191                // Wait 20 usec before checking status
 192                    mdelay(20);
 193                ulValue = readl(base+0x44);
 194            } while((ulValue & SMI_REQUEST) != 0);
 195             //printk_debug("base %x cmd %lx ret val %lx\n", tmp,Read_Cmd,ulValue);
 196            usData=(ulValue>>16);
 197
 198
 199
 200         return usData;
 201
 202 }
 203
 204 // Detect a valid PHY
 205 // If there exist a valid PHY then return TRUE, else return FALSE
 206 static int phy_detect(uint32_t base,uint16_t *PhyAddr) //BOOL PHY_Detect()
 207 {
 208     int               bFoundPhy = FALSE;
 209     uint16_t            usData;
 210     int                PhyAddress = 0;
 211
 212
 213         // Scan all PHY address(0 ~ 31) to find a valid PHY
 214         for(PhyAddress = 0; PhyAddress < 32; PhyAddress++)
 215         {
 216                 usData=phy_read(base,PhyAddress,StatusReg);  // Status register is a PHY's register(offset 01h)
 217
 218            // Found a valid PHY
 219
 220            if((usData != 0x0) && (usData != 0xffff))
 221            {
 222                bFoundPhy = TRUE;
 223                break;
 224            }
 225         }
 226
 227
 228         if(!bFoundPhy)
 229         {
 230             printk_debug("PHY not found !!!! \n");
 231         }
 232
 233        *PhyAddr=PhyAddress;
 234
 235         return bFoundPhy;
 236 }
 237
 238
 239 static void nic_init(struct device *dev)
 240 {
 241         int val;
 242         uint16_t  PhyAddr;
 243         uint32_t base;
 244         struct resource *res;
 245
 246
 247         print_debug("NIC_INIT:---------->\n");
 248
 249
 250 //-------------- enable NIC (SiS19x) -------------------------
 251 {
 252         uint8_t  temp8;
 253         int i=0;
 254         while(SiS_SiS191_init[i][0] != 0)
 255         {
 256                 temp8 = pci_read_config8(dev, SiS_SiS191_init[i][0]);
 257                 temp8 &= SiS_SiS191_init[i][1];
 258                 temp8 |= SiS_SiS191_init[i][2];
 259                 pci_write_config8(dev, SiS_SiS191_init[i][0], temp8);
 260                 i++;
 261         };
 262 }
 263 //-----------------------------------------------------------
 264
 265 {
 266         unsigned long  i;
 267         unsigned long ulValue;
 268
 269         res = find_resource(dev, 0x10);
 270
 271         if(!res)
 272         {
 273                 printk_debug("NIC Cannot find resource..\r\n");
 274                 return;
 275         }
 276         base = res->base;
 277         printk_debug("NIC base address %lx\n",base);
 278
 279         if(!(val=phy_detect(base,&PhyAddr)))
 280         {
 281                printk_debug("PHY detect fail !!!!\r\n");
 282                 return;
 283         }
 284
 285         ulValue=readl(base + 0x38L);   //  check EEPROM existing
 286
 287         if((ulValue & 0x0002))
 288         {
 289
 290           //    read MAC address from EEPROM at first
 291
 292           //    if that is valid we will use that
 293
 294                         printk_debug("EEPROM contents %x \n",ReadEEprom( dev,  base,  0LL));
 295                         for(i=0;i<3;i++) {
 296                                 //status = smbus_read_byte(dev_eeprom, i);
 297                                 ulValue=ReadEEprom( dev,  base,  i+3L);
 298                                 if (ulValue ==0x10000) break;  // error
 299
 300                                 MacAddr[i] =ulValue & 0xFFFF;
 301
 302                         }
 303         }else{
 304                  // read MAC address from firmware
 305                  printk_debug("EEPROM invalid!!\nReg 0x38h=%.8lx \n",ulValue);
 306                  MacAddr[0]=readw(0xffffffc0); // mac address store at here
 307                  MacAddr[1]=readw(0xffffffc2);
 308                  MacAddr[2]=readw(0xffffffc4);
 309         }
 310
 311         set_apc(dev);
 312
 313         readApcMacAddr();
 314
 315 #if DEBUG_NIC
 316 {
 317         int i;
 318
 319         print_debug("****** NIC PCI config ******");
 320         print_debug("\n    03020100  07060504  0B0A0908  0F0E0D0C");
 321
 322         for(i=0;i<0xff;i+=4){
 323                 if((i%16)==0){
 324                         print_debug("\r\n");
 325                         print_debug_hex8(i);
 326                         print_debug(": ");
 327                 }
 328                 print_debug_hex32(pci_read_config32(dev,i));
 329                 print_debug("  ");
 330         }
 331         print_debug("\r\n");
 332 }
 333
 334
 335 #endif
 336
 337 }
 338
 339 print_debug("NIC_INIT:<----------\n");
 340 return;
 341
 342
 343 }
 344
 345 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 346 {
 347         pci_write_config32(dev, 0x40,
 348                 ((device & 0xffff) << 16) | (vendor & 0xffff));
 349 }
 350
 351 static struct pci_operations lops_pci = {
 352         .set_subsystem  = lpci_set_subsystem,
 353 };
 354
 355 static struct device_operations nic_ops  = {
 356         .read_resources = pci_dev_read_resources,
 357         .set_resources  = pci_dev_set_resources,
 358         .enable_resources       = pci_dev_enable_resources,
 359         .init           = nic_init,
 360         .scan_bus       = 0,
 361 //      .enable         = sis966_enable,
 362         .ops_pci        = &lops_pci,
 363 };
 364
 365 static const struct pci_driver nic_driver __pci_driver = {
 366         .ops    = &nic_ops,
 367         .vendor = PCI_VENDOR_ID_SIS,
 368         .device = PCI_DEVICE_ID_SIS_SIS966_NIC,
 369 };