src/southbridge/sis/sis966/sis966_lpc.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2003 Linux Networx
   5  * Copyright (C) 2003 SuSE Linux AG
   6  * Copyright (C) 2004 Tyan Computer
   7  * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
   8  * Copyright (C) 2006,2007 AMD
   9  * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
  10  * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
  11  * Written by Morgan Tsai <my_tsai@sis.com> for SiS.
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License as published by
  15  * the Free Software Foundation; either version 2 of the License, or
  16  * (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  26  */
  27
  28 #include <console/console.h>
  29 #include <device/device.h>
  30 #include <device/pci.h>
  31 #include <device/pnp.h>
  32 #include <device/pci_ids.h>
  33 #include <device/pci_ops.h>
  34 #include <pc80/mc146818rtc.h>
  35 #include <pc80/isa-dma.h>
  36 #include <bitops.h>
  37 #include <arch/io.h>
  38 #include <arch/ioapic.h>
  39 #include <cpu/x86/lapic.h>
  40 #include <stdlib.h>
  41 #include "sis966.h"
  42 #include <pc80/keyboard.h>
  43
  44 #define NMI_OFF 0
  45
  46 // 0x7a or e3
  47 #define PREVIOUS_POWER_STATE    0x7A
  48
  49 #define MAINBOARD_POWER_OFF     0
  50 #define MAINBOARD_POWER_ON      1
  51 #define SLOW_CPU_OFF    0
  52 #define SLOW_CPU__ON    1
  53
  54 #ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
  55 #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL      MAINBOARD_POWER_ON
  56 #endif
  57
  58 #undef SLAVE_INIT
  59
  60 static void lpc_common_init(device_t dev)
  61 {
  62         uint8_t byte;
  63         uint32_t ioapic_base;
  64
  65         /* IO APIC initialization */
  66         byte = pci_read_config8(dev, 0x74);
  67         byte |= (1<<0); // enable APIC
  68         pci_write_config8(dev, 0x74, byte);
  69         ioapic_base = pci_read_config32(dev, PCI_BASE_ADDRESS_1); // 0x14
  70
  71         setup_ioapic(ioapic_base, 0); // Don't rename IO APIC ID
  72 }
  73
  74 #ifdef SLAVE_INIT
  75 static void lpc_slave_init(device_t dev)
  76 {
  77         lpc_common_init(dev);
  78 }
  79 #endif
  80
  81 static void lpc_usb_legacy_init(device_t dev)
  82 {
  83     uint16_t acpi_base;
  84
  85     acpi_base = (pci_read_config8(dev,0x75) << 8);
  86
  87     outb(inb(acpi_base + 0xbb) |0x80, acpi_base + 0xbb);
  88     outb(inb(acpi_base + 0xba) |0x80, acpi_base + 0xba);
  89 }
  90
  91 static void lpc_init(device_t dev)
  92 {
  93          uint8_t byte;
  94          uint8_t byte_old;
  95          int on;
  96          int nmi_option;
  97
  98         printk(BIOS_DEBUG, "LPC_INIT -------->\n");
  99         pc_keyboard_init(0);
 100
 101         lpc_usb_legacy_init(dev);
 102          lpc_common_init(dev);
 103
 104         /* power after power fail */
 105
 106
 107         on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
 108         get_option(&on, "power_on_after_fail");
 109         byte = pci_read_config8(dev, PREVIOUS_POWER_STATE);
 110         byte &= ~0x40;
 111         if (!on) {
 112                 byte |= 0x40;
 113         }
 114         pci_write_config8(dev, PREVIOUS_POWER_STATE, byte);
 115         printk(BIOS_INFO, "set power %s after power fail\n", on?"on":"off");
 116
 117         /* Throttle the CPU speed down for testing */
 118         on = SLOW_CPU_OFF;
 119         get_option(&on, "slow_cpu");
 120         if(on) {
 121                 uint16_t pm10_bar;
 122                 uint32_t dword;
 123                 pm10_bar = (pci_read_config16(dev, 0x60)&0xff00);
 124                 outl(((on<<1)+0x10)  ,(pm10_bar + 0x10));
 125                 dword = inl(pm10_bar + 0x10);
 126                 on = 8-on;
 127                 printk(BIOS_DEBUG, "Throttling CPU %2d.%1.1d percent.\n",
 128                                 (on*12)+(on>>1),(on&1)*5);
 129         }
 130
 131         /* Enable Error reporting */
 132         /* Set up sync flood detected */
 133         byte = pci_read_config8(dev, 0x47);
 134         byte |= (1 << 1);
 135         pci_write_config8(dev, 0x47, byte);
 136
 137         /* Set up NMI on errors */
 138         byte = inb(0x70); // RTC70
 139         byte_old = byte;
 140         nmi_option = NMI_OFF;
 141         get_option(&nmi_option, "nmi");
 142         if (nmi_option) {
 143                 byte &= ~(1 << 7); /* set NMI */
 144         } else {
 145                 byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW
 146         }
 147         if( byte != byte_old) {
 148                 outb(byte, 0x70);
 149         }
 150
 151         /* Initialize the real time clock */
 152         rtc_init(0);
 153
 154         /* Initialize isa dma */
 155         isa_dma_init();
 156
 157         printk(BIOS_DEBUG, "LPC_INIT <--------\n");
 158 }
 159
 160 static void sis966_lpc_read_resources(device_t dev)
 161 {
 162         struct resource *res;
 163
 164         /* Get the normal pci resources of this device */
 165         pci_dev_read_resources(dev); // We got one for APIC, or one more for TRAP
 166
 167         /* Add an extra subtractive resource for both memory and I/O. */
 168         res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
 169         res->base = 0;
 170         res->size = 0x1000;
 171         res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
 172                      IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 173
 174         res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
 175         res->base = 0xff800000;
 176         res->size = 0x00800000; /* 8 MB for flash */
 177         res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
 178                      IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 179
 180         res = new_resource(dev, 3); /* IOAPIC */
 181         res->base = IO_APIC_ADDR;
 182         res->size = 0x00001000;
 183         res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 184 }
 185
 186 /**
 187  * Enable resources for children devices.
 188  *
 189  * @param dev The device whos children's resources are to be enabled.
 190  */
 191 static void sis966_lpc_enable_childrens_resources(device_t dev)
 192 {
 193         struct bus *link;
 194         uint32_t reg, reg_var[4];
 195         int i;
 196         int var_num = 0;
 197
 198         reg = pci_read_config32(dev, 0xa0);
 199
 200         for (link = dev->link_list; link; link = link->next) {
 201                 device_t child;
 202                 for (child = link->children; child; child = child->sibling) {
 203                         if(child->enabled && (child->path.type == DEVICE_PATH_PNP)) {
 204                                 struct resource *res;
 205                                 for(res = child->resource_list; res; res = res->next) {
 206                                         unsigned long base, end; // don't need long long
 207                                         if(!(res->flags & IORESOURCE_IO)) continue;
 208                                         base = res->base;
 209                                         end = resource_end(res);
 210                                         printk(BIOS_DEBUG, "sis966 lpc decode:%s, base=0x%08lx, end=0x%08lx\n",dev_path(child),base, end);
 211                                         switch(base) {
 212                                         case 0x3f8: // COM1
 213                                                 reg |= (1<<0);  break;
 214                                         case 0x2f8: // COM2
 215                                                 reg |= (1<<1);  break;
 216                                         case 0x378: // Parallal 1
 217                                                 reg |= (1<<24); break;
 218                                         case 0x3f0: // FD0
 219                                                 reg |= (1<<20); break;
 220                                         case 0x220:  // Aduio 0
 221                                                 reg |= (1<<8);  break;
 222                                         case 0x300:  // Midi 0
 223                                                 reg |= (1<<12); break;
 224                                         }
 225                                         if( (base == 0x290) || (base >= 0x400)) {
 226                                                 if(var_num>=4) continue; // only 4 var ; compact them ?
 227                                                 reg |= (1<<(28+var_num));
 228                                                 reg_var[var_num++] = (base & 0xffff)|((end & 0xffff)<<16);
 229                                         }
 230                                 }
 231                         }
 232                 }
 233         }
 234         pci_write_config32(dev, 0xa0, reg);
 235         for(i=0;i<var_num;i++) {
 236                 pci_write_config32(dev, 0xa8 + i*4, reg_var[i]);
 237         }
 238
 239
 240 }
 241
 242 static void sis966_lpc_enable_resources(device_t dev)
 243 {
 244         pci_dev_enable_resources(dev);
 245         sis966_lpc_enable_childrens_resources(dev);
 246 }
 247
 248 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 249 {
 250         pci_write_config32(dev, 0x40,
 251                 ((device & 0xffff) << 16) | (vendor & 0xffff));
 252 }
 253
 254 static struct pci_operations lops_pci = {
 255         .set_subsystem  = lpci_set_subsystem,
 256 };
 257
 258 static struct device_operations lpc_ops  = {
 259         .read_resources = sis966_lpc_read_resources,
 260         .set_resources  = pci_dev_set_resources,
 261         .enable_resources       = sis966_lpc_enable_resources,
 262         .init           = lpc_init,
 263         .scan_bus       = scan_static_bus,
 264 //      .enable         = sis966_enable,
 265         .ops_pci        = &lops_pci,
 266 };
 267
 268 static const struct pci_driver lpc_driver __pci_driver = {
 269         .ops    = &lpc_ops,
 270         .vendor = PCI_VENDOR_ID_SIS,
 271         .device = PCI_DEVICE_ID_SIS_SIS966_LPC,
 272 };
 273
 274 #ifdef SLAVE_INIT // No device?
 275 static struct device_operations lpc_slave_ops  = {
 276         .read_resources = sis966_lpc_read_resources,
 277         .set_resources  = pci_dev_set_resources,
 278         .enable_resources       = pci_dev_enable_resources,
 279         .init           = lpc_slave_init,
 280 //      .enable         = sis966_enable,
 281         .ops_pci        = &lops_pci,
 282 };
 283 #endif