src/southbridge/sis/sis966/sis966_lpc.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2003 Linux Networx
   5  * Copyright (C) 2003 SuSE Linux AG
   6  * Copyright (C) 2004 Tyan Computer
   7  * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
   8  * Copyright (C) 2006,2007 AMD
   9  * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
  10  * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
  11  * Written by Morgan Tsai <my_tsai@sis.com> for SiS.
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License as published by
  15  * the Free Software Foundation; either version 2 of the License, or
  16  * (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  26  */
  27
  28 #include <console/console.h>
  29 #include <device/device.h>
  30 #include <device/pci.h>
  31 #include <device/pnp.h>
  32 #include <device/pci_ids.h>
  33 #include <device/pci_ops.h>
  34 #include <pc80/mc146818rtc.h>
  35 #include <pc80/isa-dma.h>
  36 #include <bitops.h>
  37 #include <arch/io.h>
  38 #include <arch/ioapic.h>
  39 #include <cpu/x86/lapic.h>
  40 #include <stdlib.h>
  41 #include "sis966.h"
  42 #include <pc80/keyboard.h>
  43
  44 #define NMI_OFF 0
  45
  46 // 0x7a or e3
  47 #define PREVIOUS_POWER_STATE    0x7A
  48
  49 #define MAINBOARD_POWER_OFF     0
  50 #define MAINBOARD_POWER_ON      1
  51 #define SLOW_CPU_OFF    0
  52 #define SLOW_CPU__ON    1
  53
  54 #ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
  55 #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL      MAINBOARD_POWER_ON
  56 #endif
  57
  58 static void lpc_common_init(device_t dev)
  59 {
  60         uint8_t byte;
  61         uint32_t ioapic_base;
  62
  63         /* IO APIC initialization */
  64         byte = pci_read_config8(dev, 0x74);
  65         byte |= (1<<0); // enable APIC
  66         pci_write_config8(dev, 0x74, byte);
  67         ioapic_base = pci_read_config32(dev, PCI_BASE_ADDRESS_1); // 0x14
  68
  69         setup_ioapic(ioapic_base, 0); // Don't rename IO APIC ID
  70 }
  71
  72 static void lpc_slave_init(device_t dev)
  73 {
  74         lpc_common_init(dev);
  75 }
  76
  77
  78 static void lpc_usb_legacy_init(device_t dev)
  79 {
  80     uint16_t acpi_base;
  81
  82     acpi_base = (pci_read_config8(dev,0x75) << 8);
  83
  84     outb(inb(acpi_base + 0xbb) |0x80, acpi_base + 0xbb);
  85     outb(inb(acpi_base + 0xba) |0x80, acpi_base + 0xba);
  86 }
  87
  88 static void lpc_init(device_t dev)
  89 {
  90          uint8_t byte;
  91          uint8_t byte_old;
  92          int on;
  93          int nmi_option;
  94
  95         printk_debug("LPC_INIT -------->\n");
  96         pc_keyboard_init(0);
  97
  98         lpc_usb_legacy_init(dev);
  99          lpc_common_init(dev);
 100
 101         /* power after power fail */
 102
 103
 104         on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
 105         get_option(&on, "power_on_after_fail");
 106         byte = pci_read_config8(dev, PREVIOUS_POWER_STATE);
 107         byte &= ~0x40;
 108         if (!on) {
 109                 byte |= 0x40;
 110         }
 111         pci_write_config8(dev, PREVIOUS_POWER_STATE, byte);
 112         printk_info("set power %s after power fail\n", on?"on":"off");
 113
 114         /* Throttle the CPU speed down for testing */
 115         on = SLOW_CPU_OFF;
 116         get_option(&on, "slow_cpu");
 117         if(on) {
 118                 uint16_t pm10_bar;
 119                 uint32_t dword;
 120                 pm10_bar = (pci_read_config16(dev, 0x60)&0xff00);
 121                 outl(((on<<1)+0x10)  ,(pm10_bar + 0x10));
 122                 dword = inl(pm10_bar + 0x10);
 123                 on = 8-on;
 124                 printk_debug("Throttling CPU %2d.%1.1d percent.\n",
 125                                 (on*12)+(on>>1),(on&1)*5);
 126         }
 127
 128         /* Enable Error reporting */
 129         /* Set up sync flood detected */
 130         byte = pci_read_config8(dev, 0x47);
 131         byte |= (1 << 1);
 132         pci_write_config8(dev, 0x47, byte);
 133
 134         /* Set up NMI on errors */
 135         byte = inb(0x70); // RTC70
 136         byte_old = byte;
 137         nmi_option = NMI_OFF;
 138         get_option(&nmi_option, "nmi");
 139         if (nmi_option) {
 140                 byte &= ~(1 << 7); /* set NMI */
 141         } else {
 142                 byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW
 143         }
 144         if( byte != byte_old) {
 145                 outb(byte, 0x70);
 146         }
 147
 148         /* Initialize the real time clock */
 149         rtc_init(0);
 150
 151         /* Initialize isa dma */
 152         isa_dma_init();
 153
 154         printk_debug("LPC_INIT <--------\n");
 155 }
 156
 157 static void sis966_lpc_read_resources(device_t dev)
 158 {
 159         struct resource *res;
 160
 161         /* Get the normal pci resources of this device */
 162         pci_dev_read_resources(dev); // We got one for APIC, or one more for TRAP
 163
 164         /* Add an extra subtractive resource for both memory and I/O. */
 165         res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
 166         res->base = 0;
 167         res->size = 0x1000;
 168         res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
 169                      IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 170
 171         res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
 172         res->base = 0xff800000;
 173         res->size = 0x00800000; /* 8 MB for flash */
 174         res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
 175                      IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 176
 177         res = new_resource(dev, 3); /* IOAPIC */
 178         res->base = 0xfec00000;
 179         res->size = 0x00001000;
 180         res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 181 }
 182
 183 /**
 184  * @brief Enable resources for children devices
 185  *
 186  * @param dev the device whos children's resources are to be enabled
 187  *
 188  * This function is call by the global enable_resources() indirectly via the
 189  * device_operation::enable_resources() method of devices.
 190  *
 191  * Indirect mutual recursion:
 192  *      enable_childrens_resources() -> enable_resources()
 193  *      enable_resources() -> device_operation::enable_resources()
 194  *      device_operation::enable_resources() -> enable_children_resources()
 195  */
 196 static void sis966_lpc_enable_childrens_resources(device_t dev)
 197 {
 198         unsigned link;
 199         uint32_t reg, reg_var[4];
 200         int i;
 201         int var_num = 0;
 202
 203         reg = pci_read_config32(dev, 0xa0);
 204
 205         for (link = 0; link < dev->links; link++) {
 206                 device_t child;
 207                 for (child = dev->link[link].children; child; child = child->sibling) {
 208                         enable_resources(child);
 209                         if(child->enabled && (child->path.type == DEVICE_PATH_PNP)) {
 210                                 for(i=0;i<child->resources;i++) {
 211                                         struct resource *res;
 212                                         unsigned long base, end; // don't need long long
 213                                         res = &child->resource[i];
 214                                         if(!(res->flags & IORESOURCE_IO)) continue;
 215                                         base = res->base;
 216                                         end = resource_end(res);
 217                                         printk_debug("sis966 lpc decode:%s, base=0x%08x, end=0x%08x\n",dev_path(child),base, end);
 218                                         switch(base) {
 219                                         case 0x3f8: // COM1
 220                                                 reg |= (1<<0);  break;
 221                                         case 0x2f8: // COM2
 222                                                 reg |= (1<<1);  break;
 223                                         case 0x378: // Parallal 1
 224                                                 reg |= (1<<24); break;
 225                                         case 0x3f0: // FD0
 226                                                 reg |= (1<<20); break;
 227                                         case 0x220:  // Aduio 0
 228                                                 reg |= (1<<8);  break;
 229                                         case 0x300:  // Midi 0
 230                                                 reg |= (1<<12); break;
 231                                         }
 232                                         if( (base == 0x290) || (base >= 0x400)) {
 233                                                 if(var_num>=4) continue; // only 4 var ; compact them ?
 234                                                 reg |= (1<<(28+var_num));
 235                                                 reg_var[var_num++] = (base & 0xffff)|((end & 0xffff)<<16);
 236                                         }
 237                                 }
 238                         }
 239                 }
 240         }
 241         pci_write_config32(dev, 0xa0, reg);
 242         for(i=0;i<var_num;i++) {
 243                 pci_write_config32(dev, 0xa8 + i*4, reg_var[i]);
 244         }
 245
 246
 247 }
 248
 249 static void sis966_lpc_enable_resources(device_t dev)
 250 {
 251         pci_dev_enable_resources(dev);
 252         sis966_lpc_enable_childrens_resources(dev);
 253 }
 254
 255 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 256 {
 257         pci_write_config32(dev, 0x40,
 258                 ((device & 0xffff) << 16) | (vendor & 0xffff));
 259 }
 260
 261 static struct pci_operations lops_pci = {
 262         .set_subsystem  = lpci_set_subsystem,
 263 };
 264
 265 static struct device_operations lpc_ops  = {
 266         .read_resources = sis966_lpc_read_resources,
 267         .set_resources  = pci_dev_set_resources,
 268         .enable_resources       = sis966_lpc_enable_resources,
 269         .init           = lpc_init,
 270         .scan_bus       = scan_static_bus,
 271 //      .enable         = sis966_enable,
 272         .ops_pci        = &lops_pci,
 273 };
 274 static const struct pci_driver lpc_driver __pci_driver = {
 275         .ops    = &lpc_ops,
 276         .vendor = PCI_VENDOR_ID_SIS,
 277         .device = PCI_DEVICE_ID_SIS_SIS966_LPC,
 278 };
 279
 280 static struct device_operations lpc_slave_ops  = {
 281         .read_resources = sis966_lpc_read_resources,
 282         .set_resources  = pci_dev_set_resources,
 283         .enable_resources       = pci_dev_enable_resources,
 284         .init           = lpc_slave_init,
 285 //      .enable         = sis966_enable,
 286         .ops_pci        = &lops_pci,
 287 };