src/southbridge/sis/sis966/sis966_early_smbus.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
   5  * Written by Morgan Tsai <my_tsai@sis.com> for SiS.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  20  */
  21
  22 #include "sis966_smbus.h"
  23
  24 #define SMBUS0_IO_BASE  0x8D0
  25
  26 static const uint8_t SiS_LPC_init[34][3]={
  27 {0x04, 0xF8, 0x07},                                     //Reg 0x04
  28 {0x45, 0x00, 0x00},                                     //Reg 0x45                      //Enable Rom Flash
  29 {0x46, 0x00, 0x3D},                                     //Reg 0x46
  30 {0x47, 0x00, 0xDD},                                     //Reg 0x47
  31 {0x48, 0x00, 0x12},                                     //Reg 0x48
  32 {0x64, 0x00, 0xFF},                                     //Reg 0x64
  33 {0x65, 0x00, 0xC1},                                     //Reg 0x65
  34 {0x68, 0x00, 0x89},                                     //Reg 0x68                      //SB.ASM, START POST
  35 {0x69, 0x00, 0x80},                                     //Reg 0x69
  36 {0x6B, 0x00, 0x00},                                     //Reg 0x6B                      //SBBB.ASM
  37 {0x6C, 0xFF, 0x97},                                     //Reg 0x6C                      //SBBB.ASM
  38 {0x6E, 0x00, 0x00},                                     //Reg 0x6E                      //SBBB.ASM                      But in Early Post sets 0x04.
  39 {0x6F, 0xFF, 0x14},                                     //Reg 0x6F                      //SBBB.ASM
  40 {0x77, 0x00, 0x0E},                                     //Reg 0x77                      //SBOEM.ASM, EARLY POST
  41 {0x78, 0x00, 0x20},                                     //Reg 0x78
  42 {0x7B, 0x00, 0x88},                                     //Reg 0x7B
  43 {0x7F, 0x00, 0x40},                                     //Reg 0x7F                      //SBOEM.ASM, EARLY POST
  44 {0xC1, 0x00, 0xF0},                                     //Reg 0xC1
  45 {0xC2, 0x00, 0x01},                                     //Reg 0xC2
  46 {0xC3, 0x00, 0x00},                                     //Reg 0xC3                      //NBAGPBB.ASM
  47 {0xC9, 0x00, 0x80},                                     //Reg 0xC9
  48 {0xCF, 0x00, 0x45},                                     //Reg 0xCF
  49 {0xD0, 0x00, 0x02},                                     //Reg 0xD0
  50 {0xD4, 0x00, 0x44},                                     //Reg 0xD4
  51 {0xD5, 0x00, 0x62},                                     //Reg 0xD5
  52 {0xD6, 0x00, 0x32},                                     //Reg 0xD6
  53 {0xD8, 0x00, 0x45},                                     //Reg 0xD8
  54 {0xDA, 0x00, 0xDA},                                     //Reg 0xDA
  55 {0xDB, 0x00, 0x61},                                     //Reg 0xDB
  56 {0xDC, 0x00, 0xAA},                                     //Reg 0xDC
  57 {0xDD, 0x00, 0xAA},                                     //Reg 0xDD
  58 {0xDE, 0x00, 0xAA},                                     //Reg 0xDE
  59 {0xDF, 0x00, 0xAA},                                     //Reg 0xDF
  60 {0x00, 0x00, 0x00}                                      //End of table
  61 };
  62
  63 static const uint8_t    SiS_NBPCIE_init[43][3]={
  64 {0x3D, 0x00, 0x00},                                     //Reg 0x3D
  65 {0x1C, 0xFE, 0x01},                                     //Reg 0x1C
  66 {0x1D, 0xFE, 0x01},                                     //Reg 0x1D
  67 {0x24, 0xFE, 0x01},                                     //Reg 0x24
  68 {0x26, 0xFE, 0x01},                                     //Reg 0x26
  69 {0x40, 0xFF, 0x10},                                     //Reg 0x40
  70 {0x43, 0xFF, 0x78},                                     //Reg 0x43
  71 {0x44, 0xFF, 0x02},                                     //Reg 0x44
  72 {0x45, 0xFF, 0x10},                                     //Reg 0x45
  73 {0x48, 0xFF, 0x52},                                     //Reg 0x48
  74 {0x49, 0xFF, 0xE3},                                     //Reg 0x49
  75 {0x5A, 0x00, 0x00},                                     //Reg 0x4A
  76 {0x4B, 0x00, 0x16},                                     //Reg 0x4B
  77 {0x4C, 0x00, 0x80},                                     //Reg 0x4C
  78 {0x4D, 0x00, 0x02},                                     //Reg 0x4D
  79 {0x4E, 0x00, 0x00},                                     //Reg 0x4E
  80 {0x5C, 0x00, 0x52},                                     //Reg 0x5C
  81 {0x5E, 0x00, 0x10},                                     //Reg 0x5E
  82 {0x34, 0x00, 0xD0},                                     //Reg 0x34
  83 {0xD0, 0x00, 0x01},                                     //Reg 0xD0
  84 {0x4F, 0x00, 0x80},                                     //Reg 0x4F
  85 {0xA1, 0x00, 0xF4},                                     //Reg 0xA1
  86 {0xA2, 0x7F, 0x00},                                     //Reg 0xA2
  87 {0xBD, 0x00, 0xA0},                                     //Reg 0xBD
  88 {0xD1, 0xFF, 0x00},                                     //Reg 0xD1
  89 {0xD3, 0xFE, 0x01},                                     //Reg 0xD3
  90 {0xD4, 0x18, 0x20},                                     //Reg 0xD4
  91 {0xD5, 0xF0, 0x00},                                     //Reg 0xD5
  92 {0xDD, 0xFF, 0x00},                                     //Reg 0xDD
  93 {0xDE, 0xEC, 0x10},                                     //Reg 0xDE
  94 {0xDF, 0xFF, 0x00},                                     //Reg 0xDF
  95 {0xE0, 0xF7, 0x00},                                     //Reg 0xE0
  96 {0xE3, 0xEF, 0x10},                                     //Reg 0xE3
  97 {0xE4, 0x7F, 0x80},                                     //Reg 0xE4
  98 {0xE5, 0xFF, 0x00},                                     //Reg 0xE5
  99 {0xE6, 0x06, 0x00},                                     //Reg 0xE6
 100 {0xE7, 0xFF, 0x00},                                     //Reg 0xE7
 101 {0xF5, 0x00, 0x00},                                     //Reg 0xF5
 102 {0xF6, 0x3F, 0x00},                                     //Reg 0xF6
 103 {0xF7, 0xFF, 0x00},                                     //Reg 0xF7
 104 {0xFD, 0xFF, 0x00},                                     //Reg 0xFD
 105 {0x4F, 0x00, 0x00},                                     //Reg 0x4F
 106 {0x00, 0x00, 0x00}                                      //End of table
 107 };
 108
 109 static const uint8_t    SiS_ACPI_init[10][3]={
 110 {0x1B, 0xBF, 0x40},                                     //Reg 0x1B
 111 {0x84, 0x00, 0x0E},                                     //Reg 0x84
 112 {0x85, 0x00, 0x29},                                     //Reg 0x85
 113 {0x86, 0x00, 0xCB},                                     //Reg 0x86
 114 {0x87, 0x00, 0x55},                                     //Reg 0x87
 115 {0x6B, 0x00, 0x00},                                     //Reg 0x6B
 116 {0x6C, 0x68, 0x97},                                     //Reg 0x6C
 117 {0x6E, 0x00, 0x00},                                     //Reg 0x6E
 118 {0x6F, 0xFF, 0x14},                                     //Reg 0x6F
 119 {0x00, 0x00, 0x00}                                      //End of table
 120 };
 121
 122 static const uint8_t    SiS_SBPCIE_init[13][3]={
 123 {0x48, 0x00 ,0x07},                                     //Reg 0x48
 124 {0x49, 0x00 ,0x06},                                     //Reg 0x49
 125 {0x4A, 0x00 ,0x0C},                                     //Reg 0x4A
 126 {0x4B, 0x00 ,0x00},                                     //Reg 0x4B
 127 {0x4E, 0x00 ,0x20},                                     //Reg 0x4E
 128 {0x1C, 0x00 ,0xF1},                                     //Reg 0x1C
 129 {0x1D, 0x00 ,0x01},                                     //Reg 0x1D
 130 {0x24, 0x00 ,0x01},                                     //Reg 0x24
 131 {0x26, 0x00 ,0x01},                                     //Reg 0x26
 132 {0xF6, 0x00 ,0x02},                                     //Reg 0xF6
 133 {0xF7, 0x00 ,0xC8},                                     //Reg 0xF7
 134 {0x5B, 0x00 ,0x40},                                     //Reg 0x5B
 135 {0x00, 0x00, 0x00}                                      //End of table
 136 };
 137
 138 static const uint8_t    SiS_NB_init[56][3]={
 139 {0x04, 0x00 ,0x07},                                     //Reg 0x04
 140 {0x05, 0x00 ,0x00},                                     //Reg 0x05 // alex
 141 {0x0D, 0x00 ,0x20},                                     //Reg 0x0D
 142 {0x2C, 0x00 ,0x39},                                     //Reg 0x2C
 143 {0x2D, 0x00 ,0x10},                                     //Reg 0x2D
 144 {0x2E, 0x00 ,0x61},                                     //Reg 0x2E
 145 {0x2F, 0x00 ,0x07},                                     //Reg 0x2F
 146 {0x34, 0x00 ,0xA0},                                     //Reg 0x34
 147 {0x40, 0x00 ,0x36},                                     //Reg 0x40
 148 {0x42, 0x00 ,0xB9},                                     //Reg 0x42
 149 {0x43, 0x00 ,0x8B},                                     //Reg 0x43
 150 {0x44, 0x00 ,0x05},                                     //Reg 0x44
 151 {0x45, 0x00 ,0xFF},                                     //Reg 0x45
 152 {0x46, 0x00 ,0x90},                                     //Reg 0x46
 153 {0x47, 0x00 ,0xA0},                                     //Reg 0x47
 154 //{0x4C, 0xFF ,0x09},                                   //Reg 0x4C // SiS307 enable
 155 {0x4E, 0x00 ,0x00},                                     //Reg 0x4E
 156 {0x4F, 0x00 ,0x02},                                     //Reg 0x4F
 157 {0x5B, 0x00 ,0x44},                                     //Reg 0x5B
 158 {0x5D, 0x00 ,0x00},                                     //Reg 0x5D
 159 {0x5E, 0x00 ,0x25},                                     //Reg 0x5E
 160 {0x61, 0x00 ,0xB0},                                     //Reg 0x61
 161 {0x65, 0x00 ,0xB0},                                     //Reg 0x65
 162 {0x68, 0x00 ,0x4C},                                     //Reg 0x68
 163 {0x69, 0x00 ,0xD0},                                     //Reg 0x69
 164 {0x6B, 0x00 ,0x07},                                     //Reg 0x6B
 165 {0x6C, 0x00 ,0xDD},                                     //Reg 0x6C
 166 {0x6D, 0x00 ,0xAD},                                     //Reg 0x6D
 167 {0x6E, 0x00 ,0xE8},                                     //Reg 0x6E
 168 {0x6F, 0x00 ,0x4D},                                     //Reg 0x6F
 169 {0x70, 0x00 ,0x00},                                     //Reg 0x70
 170 {0x71, 0x00 ,0x80},                                     //Reg 0x71
 171 {0x72, 0x00 ,0x00},                                     //Reg 0x72
 172 {0x73, 0x00 ,0x00},                                     //Reg 0x73
 173 {0x74, 0x00 ,0x01},                                     //Reg 0x74
 174 {0x75, 0x00 ,0x10},                                     //Reg 0x75
 175 {0x7E, 0x00 ,0x29},                                     //Reg 0x7E
 176 {0x8B, 0x00 ,0x10},                                     //Reg 0x8B
 177 {0x8D, 0x00 ,0x03},                                     //Reg 0x8D
 178 {0xA1, 0x00 ,0xD0},                                     //Reg 0xA1
 179 {0xA2, 0x00 ,0x30},                                     //Reg 0xA2
 180 {0xA4, 0x00 ,0x0B},                                     //Reg 0xA4
 181 {0xA9, 0x00 ,0x02},                                     //Reg 0xA9
 182 {0xB0, 0x00 ,0x30},                                     //Reg 0xB0
 183 {0xB4, 0x00 ,0x30},                                     //Reg 0xB4
 184 {0x90, 0x00 ,0x00},                                     //Reg 0x90
 185 {0x91, 0x00 ,0x00},                                     //Reg 0x91
 186 {0x92, 0x00 ,0x00},                                     //Reg 0x92
 187 {0x93, 0x00 ,0x00},                                     //Reg 0x93
 188 {0x94, 0x00 ,0x00},                                     //Reg 0x94
 189 {0x95, 0x00 ,0x00},                                     //Reg 0x95
 190 {0x96, 0x00 ,0x00},                                     //Reg 0x96
 191 {0x97, 0x00 ,0x00},                                     //Reg 0x97
 192 {0x98, 0x00 ,0x00},                                     //Reg 0x98
 193 {0x99, 0x00 ,0x00},                                     //Reg 0x99
 194 {0x00, 0x00, 0x00}                                      //End of table
 195 };
 196
 197 static const uint8_t SiS_NBAGP_init[34][3]={
 198 {0xCF, 0xDF, 0x00},     //HT issue
 199 {0x06, 0xDF, 0x20},
 200 {0x1E, 0xDF, 0x20},
 201 {0x50, 0x00, 0x02},
 202 {0x51, 0x00, 0x00},
 203 {0x54, 0x00, 0x09},
 204 {0x55, 0x00, 0x00},
 205 {0x56, 0x00, 0x80},
 206 {0x58, 0x00, 0x08},
 207 {0x60, 0x00, 0xB1},
 208 {0x61, 0x00, 0x02},
 209 {0x62, 0x00, 0x60},
 210 {0x63, 0x00, 0x60},
 211 {0x64, 0x00, 0xAA},
 212 {0x65, 0x00, 0x18},
 213 {0x68, 0x00, 0x23},
 214 {0x69, 0x00, 0x23},
 215 {0x6A, 0x00, 0xC8},
 216 {0x6B, 0x00, 0x08},
 217 {0x6C, 0x00, 0x00},
 218 {0x6D, 0x00, 0x00},
 219 {0x6E, 0x00, 0x08},
 220 {0x6F, 0x00, 0x00},
 221 {0xBB, 0x00, 0x00},
 222 {0xB5, 0x00, 0x30},
 223 {0xB0, 0x00, 0xDB},
 224 {0xB6, 0x00, 0x73},
 225 {0xB7, 0x00, 0x50},
 226 {0xBA, 0xBF, 0x41},
 227 {0xB4, 0x3F, 0xC0},
 228 {0xBF, 0xF9, 0x06},
 229 {0xBA, 0x00, 0x61},
 230 {0xBD, 0x7F, 0x80},
 231 {0x00, 0x00, 0x00}      //End of table
 232 };
 233
 234 static const uint8_t    SiS_ACPI_2_init[56][3]={
 235 {0x00, 0x00, 0xFF},                                     //Reg 0x00
 236 {0x01, 0x00, 0xFF},                                     //Reg 0x01
 237 {0x02, 0x00, 0x00},                                     //Reg 0x02
 238 {0x03, 0x00, 0x00},                                     //Reg 0x03
 239 {0x16, 0x00, 0x00},                                     //Reg 0x16
 240 {0x20, 0x00, 0xFF},                                     //Reg 0x20
 241 {0x21, 0x00, 0xFF},                                     //Reg 0x21
 242 {0x22, 0x00, 0x00},                                     //Reg 0x22
 243 {0x23, 0x00, 0x00},                                     //Reg 0x23
 244 {0x24, 0x00, 0x55},                                     //Reg 0x24
 245 {0x25, 0x00, 0x55},                                     //Reg 0x25
 246 {0x26, 0x00, 0x55},                                     //Reg 0x26
 247 {0x27, 0x00, 0x55},                                     //Reg 0x27
 248 {0x2A, 0x00, 0x40},                                     //Reg 0x2A
 249 {0x2B, 0x00, 0x10},                                     //Reg 0x2B
 250 {0x2E, 0x00, 0xFF},                                     //Reg 0x2E
 251 {0x30, 0x00, 0xFF},                                     //Reg 0x30
 252 {0x31, 0x00, 0xFF},                                     //Reg 0x31
 253 {0x32, 0x00, 0x00},                                     //Reg 0x32
 254 {0x33, 0x00, 0x00},                                     //Reg 0x33
 255 {0x40, 0x00, 0xFF},                                     //Reg 0x40
 256 {0x41, 0x00, 0xFF},                                     //Reg 0x41
 257 {0x42, 0x00, 0x00},                                     //Reg 0x42
 258 {0x43, 0x00, 0x00},                                     //Reg 0x43
 259 {0x4A, 0x00, 0x00},                                     //Reg 0x4A
 260 {0x4E, 0x00, 0x0F},                                     //Reg 0x4E
 261 {0x5A, 0x00, 0x00},                                     //Reg 0x5A
 262 {0x5B, 0x00, 0x00},                                     //Reg 0x5B
 263 {0x62, 0x00, 0x00},                                     //Reg 0x62
 264 {0x63, 0x00, 0x04},                                     //Reg 0x63
 265 {0x68, 0x00, 0xFF},                                     //Reg 0x68
 266 {0x76, 0x00, 0xA0},                                     //Reg 0x76
 267 {0x77, 0x00, 0x22},                                     //Reg 0x77
 268 {0x78, 0xDF, 0x20},                                     //Reg 0x78
 269 {0x7A, 0x00, 0x10},                                     //Reg 0x7A
 270 {0x7C, 0x00, 0x45},                                     //Reg 0x7C
 271 {0x7D, 0x00, 0xB8},                                     //Reg 0x7D
 272 {0x7F, 0x00, 0x00},                                     //Reg 0x7F
 273 {0x80, 0x00, 0x1C},                                     //Reg 0x80
 274 {0x82, 0x00, 0x01},                                     //Reg 0x82
 275 {0x84, 0x00, 0x0E},                                     //Reg 0x84
 276 {0x85, 0x00, 0x29},                                     //Reg 0x85
 277 {0x86, 0x00, 0xCB},                                     //Reg 0x86
 278 {0x87, 0x00, 0x55},                                     //Reg 0x87
 279 {0x88, 0x00, 0x04},                                     //Reg 0x88
 280 {0x96, 0x00, 0x80},                                     //Reg 0x96
 281 {0x99, 0x00, 0x80},                                     //Reg 0x99
 282 {0x9A, 0x00, 0x15},                                     //Reg 0x9A
 283 {0x9D, 0x00, 0x05},                                     //Reg 0x9D
 284 {0x9E, 0x00, 0x00},                                     //Reg 0x9E
 285 {0x9F, 0x00, 0x04},                                     //Reg 0x9F
 286 {0xB0, 0x00, 0x6D},                                     //Reg 0xB0
 287 {0xB1, 0x00, 0x8C},                                     //Reg 0xB1
 288 {0xB9, 0x00, 0xFF},                                     //Reg 0xB9
 289 {0xBA, 0x00, 0x3F},                                     //Reg 0xBA
 290 {0x00, 0x00, 0x00}                                      //End of table
 291 };
 292
 293 static const uint8_t    SiS_SiS1183_init[44][3]={
 294 {0x04, 0x00, 0x05},
 295 {0x09, 0x00, 0x05},
 296 {0x2C, 0x00, 0x39},
 297 {0x2D, 0x00, 0x10},
 298 {0x2E, 0x00, 0x83},
 299 {0x2F, 0x00, 0x11},
 300 {0x90, 0x00, 0x40},
 301 {0x91, 0x00, 0x00},     // set mode
 302 {0x50, 0x00, 0xA2},
 303 {0x52, 0x00, 0xA2},
 304 {0x55, 0x00, 0x96},
 305 {0x52, 0x00, 0xA2},
 306 {0x55, 0xF7, 0x00},
 307 {0x56, 0x00, 0xC0},
 308 {0x57, 0x00, 0x14},
 309 {0x67, 0x00, 0x28},
 310 {0x81, 0x00, 0xB3},
 311 {0x82, 0x00, 0x72},
 312 {0x83, 0x00, 0x40},
 313 {0x85, 0x00, 0xB3},
 314 {0x86, 0x00, 0x72},
 315 {0x87, 0x00, 0x40},
 316 {0x88, 0x00, 0xDE},     // after set mode
 317 {0x89, 0x00, 0xB3},
 318 {0x8A, 0x00, 0x72},
 319 {0x8B, 0x00, 0x40},
 320 {0x8C, 0x00, 0xDE},
 321 {0x8D, 0x00, 0xB3},
 322 {0x8E, 0x00, 0x92},
 323 {0x8F, 0x00, 0x40},
 324 {0x93, 0x00, 0x00},
 325 {0x94, 0x00, 0x80},
 326 {0x95, 0x00, 0x08},
 327 {0x96, 0x00, 0x80},
 328 {0x97, 0x00, 0x08},
 329 {0x9C, 0x00, 0x80},
 330 {0x9D, 0x00, 0x08},
 331 {0x9E, 0x00, 0x80},
 332 {0x9F, 0x00, 0x08},
 333 {0xA0, 0x00, 0x15},
 334 {0xA1, 0x00, 0x15},
 335 {0xA2, 0x00, 0x15},
 336 {0xA3, 0x00, 0x15},
 337 {0x00, 0x00, 0x00}      //End of table
 338 };
 339
 340 /*       In => Share Memory size
 341                             => 00h :    0MBytes
 342                             => 02h :   32MBytes
 343                             => 03h :   64MBytes
 344                             => 04h :  128MBytes
 345                             => Others:  Reserved
 346 */
 347 void Init_Share_Memory(uint8_t ShareSize)
 348 {
 349     device_t dev;
 350
 351     dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0);
 352     pci_write_config8(dev, 0x4C, (pci_read_config8(dev, 0x4C) & 0x1F) | (ShareSize << 5));
 353 }
 354
 355 /* In:     => Aperture size
 356                => 00h :   32MBytes
 357                => 01h :   64MBytes
 358                => 02h :  128MBytes
 359                => 03h :  256MBytes
 360                => 04h :  512MBytes
 361                => Others:  Reserved
 362 */
 363 void Init_Aper_Size(uint8_t AperSize)
 364 {
 365         device_t dev;
 366         uint16_t SiSAperSizeTable[]={0x0F38, 0x0F30, 0x0F20, 0x0F00, 0x0E00};
 367
 368         dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_AMD, 0x1103), 0);
 369         pci_write_config8(dev, 0x90, AperSize << 1);
 370
 371         dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0);
 372         pci_write_config16(dev, 0xB4, SiSAperSizeTable[AperSize]);
 373 }
 374
 375 void sis_init_stage1(void)
 376 {
 377         device_t dev;
 378         uint8_t temp8;
 379         int     i;
 380         uint8_t GUI_En;
 381
 382 // SiS_Chipset_Initialization
 383 // ========================== NB =============================
 384         dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0);
 385         i=0;
 386         while(SiS_NB_init[i][0] != 0)
 387         {                               temp8 = pci_read_config8(dev, SiS_NB_init[i][0]);
 388                                         temp8 &= SiS_NB_init[i][1];
 389                                         temp8 |= SiS_NB_init[i][2];
 390                                         pci_write_config8(dev, SiS_NB_init[i][0], temp8);
 391                                         i++;
 392         };
 393
 394 // ========================== LPC =============================
 395         dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS966_LPC), 0);
 396         i=0;
 397         while(SiS_LPC_init[i][0] != 0)
 398         {                               temp8 = pci_read_config8(dev, SiS_LPC_init[i][0]);
 399                                         temp8 &= SiS_LPC_init[i][1];
 400                                         temp8 |= SiS_LPC_init[i][2];
 401                                         pci_write_config8(dev, SiS_LPC_init[i][0], temp8);
 402                                         i++;
 403         };
 404 // ========================== ACPI =============================
 405         i=0;
 406         while(SiS_ACPI_init[i][0] != 0)
 407         {                               temp8 = inb(0x800 + SiS_ACPI_init[i][0]);
 408                                         temp8 &= SiS_ACPI_init[i][1];
 409                                         temp8 |= SiS_ACPI_init[i][2];
 410                                         outb(temp8, 0x800 + SiS_ACPI_init[i][0]);
 411                                         i++;
 412         };
 413 // ========================== NBPCIE =============================
 414         dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0);        //Disable Internal GUI enable bit
 415         temp8 = pci_read_config8(dev, 0x4C);
 416         GUI_En = temp8 & 0x10;
 417         pci_write_config8(dev, 0x4C, temp8 & (!0x10));
 418
 419         dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761_PCIE), 0);
 420         i=0;
 421         while(SiS_NBPCIE_init[i][0] != 0)
 422         {                               temp8 = pci_read_config8(dev, SiS_NBPCIE_init[i][0]);
 423                                         temp8 &= SiS_NBPCIE_init[i][1];
 424                                         temp8 |= SiS_NBPCIE_init[i][2];
 425                                         pci_write_config8(dev, SiS_NBPCIE_init[i][0], temp8);
 426                                         i++;
 427         };
 428         dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0);        //Restore Internal GUI enable bit
 429         temp8 = pci_read_config8(dev, 0x4C);
 430         pci_write_config8(dev, 0x4C, temp8 | GUI_En);
 431
 432         return;
 433 }
 434
 435
 436
 437 void sis_init_stage2(void)
 438 {
 439         device_t dev;
 440         msr_t   msr;
 441         int     i;
 442         uint8_t temp8;
 443         uint16_t temp16;
 444
 445
 446 // ========================== NB_AGP =============================
 447         dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0);   //Enable Internal GUI enable bit
 448         pci_write_config8(dev, 0x4C, pci_read_config8(dev, 0x4C) | 0x10);
 449
 450         dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_AGP), 0);
 451         i=0;
 452
 453         while(SiS_NBAGP_init[i][0] != 0)
 454         {
 455                 temp8 = pci_read_config8(dev, SiS_NBAGP_init[i][0]);
 456                 temp8 &= SiS_NBAGP_init[i][1];
 457                 temp8 |= SiS_NBAGP_init[i][2];
 458                 pci_write_config8(dev, SiS_NBAGP_init[i][0], temp8);
 459                 i++;
 460         };
 461
 462 /**
 463   *   Share Memory size
 464   *             => 00h :    0MBytes
 465   *             => 02h :   32MBytes
 466   *             => 03h :   64MBytes
 467   *             => 04h :  128MBytes
 468   *             => Others:  Reserved
 469   *
 470   *   Aperture size
 471   *             => 00h :   32MBytes
 472   *             => 01h :   64MBytes
 473   *             => 02h :  128MBytes
 474   *             => 03h :  256MBytes
 475   *             => 04h :  512MBytes
 476   *             => Others:  Reserved
 477   */
 478
 479         Init_Share_Memory(0x02);  //0x02 : 32M
 480         Init_Aper_Size(0x01);   //0x1 : 64M
 481
 482 // ========================== NB =============================
 483
 484         printk_debug("Init NorthBridge sis761 -------->\n");
 485         dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0);
 486         msr = rdmsr(0xC001001A);
 487          printk_debug("Memory Top Bound %lx\n",msr.lo );
 488
 489         temp16=(pci_read_config8(dev, 0x4C) & 0xE0) >> 5;
 490         temp16=0x0001<<(temp16-1);
 491         temp16<<=8;
 492
 493         printk_debug("Integrated VGA Shared memory size=%dM bytes\n", temp16 >> 4);
 494         pci_write_config16(dev, 0x8E, (msr.lo >> 16) -temp16*1);
 495         pci_write_config8(dev, 0x7F, 0x08);                                                                     // ACPI Base
 496         outb(inb(0x856) | 0x40, 0x856);                                                                         // Auto-Reset Function
 497
 498 // ========================== ACPI =============================
 499         i=0;
 500         printk_debug("Init ACPI -------->\n");
 501         do
 502         {                               temp8 = inb(0x800 + SiS_ACPI_2_init[i][0]);
 503                                         temp8 &= SiS_ACPI_2_init[i][1];
 504                                         temp8 |= SiS_ACPI_2_init[i][2];
 505                                         outb(temp8, 0x800 + SiS_ACPI_2_init[i][0]);
 506                                         i++;
 507         }while(SiS_ACPI_2_init[i][0] != 0);
 508
 509 // ========================== Misc =============================
 510        printk_debug("Init Misc -------->\n");
 511         dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS966_LPC), 0);
 512
 513         /* R77h Internal PCI Device Enable 1 (Power On Value = 0h)
 514          * bit5 : USB Emulation (1=enable)
 515          * bit3 : Internal Keyboard Controller Port Access Control enable (1=enable)
 516          * bit2 : Reserved
 517          * bit1 : Mask USB A20M# Event (1:K8, 0:P4/K7)
 518          */
 519         pci_write_config8(dev, 0x77, 0x2E);
 520
 521         /* R7Ch Internal PCI Device Enable 2  (Power On Value = 0h)
 522          * bit4 : SATA Controller Enable (0=enable)
 523          * bit3 : IDE Controller Enable (0=enable)
 524          * bit2 : MAC Controller Enable (0=enable)
 525          * bit1 : MODEM Controller Enable (1=disable)
 526          * bit0 : AC97 Controller Enable (1=disable)
 527          */
 528         pci_write_config8(dev, 0x7C, 0x03);
 529
 530         /* R7Eh Enable Azalia (Power On Value = 08h)
 531          * bit3 : Azalia Controller Enable (0=enable)
 532          */
 533         pci_write_config8(dev, 0x7E, 0x00);  // azalia controller enable
 534         temp8=inb(0x878)|0x4;   //bit2=1 enable Azalia  =0 enable AC97
 535         outb(temp8, 0x878);  // ACPI select AC97 or HDA controller
 536         printk_debug("Audio select %x\n",inb(0x878));
 537
 538         dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS966_SATA), 0);
 539
 540         if (!dev)
 541                 print_debug("SiS 1183 does not exist !!");
 542         // SATA Set Mode
 543         pci_write_config8(dev, 0x90, (pci_read_config8(dev, 0x90)&0x3F) | 0x40);
 544
 545 }
 546
 547
 548
 549 static void enable_smbus(void)
 550 {
 551         device_t dev;
 552         uint8_t temp8;
 553         printk_debug("enable_smbus -------->\n");
 554
 555         dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS966_LPC), 0);
 556
 557         /* set smbus iobase && enable ACPI Space*/
 558         pci_write_config16(dev, 0x74, 0x0800);                          // Set ACPI Base
 559         temp8=pci_read_config8(dev, 0x40);                                      // Enable ACPI Space
 560         pci_write_config8(dev, 0x40, temp8 | 0x80);
 561         temp8=pci_read_config8(dev, 0x76);                                      // Enable SMBUS
 562         pci_write_config8(dev, 0x76, temp8 | 0x03);
 563
 564         printk_debug("enable_smbus <--------\n");
 565 }
 566
 567 static int smbus_read_byte(unsigned device, unsigned address)
 568 {
 569         return do_smbus_read_byte(SMBUS0_IO_BASE, device, address);
 570 }
 571 static int smbus_write_byte(unsigned device, unsigned address, unsigned char val)
 572 {
 573         return do_smbus_write_byte(SMBUS0_IO_BASE, device, address, val);
 574 }
 575