2 * This file is part of the coreboot project.
4 * Copyright (C) 2012 Rudolf Marek <r.marek@assembler.cz>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <arch/romcc_io.h>
22 #include <device/pci_def.h>
24 static void bootblock_southbridge_init(void) {
26 tmp = pci_read_config32(PCI_DEV(0,7,0), 0x40);
27 /* decode all flash ranges */
28 pci_write_config32(PCI_DEV(0,7,0), 0x40, tmp | 0x07ff0000);