2 * This file is part of the coreboot project.
4 * Copyright (C) 2004 Tyan Computer
5 * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
6 * Copyright (C) 2006,2007 AMD
7 * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 #include <console/console.h>
25 #include <device/device.h>
26 #include <device/resource.h>
27 #include <device/pci.h>
28 #include <device/pci_ids.h>
29 #include <device/pci_ops.h>
32 static void pci_init(struct device *dev)
36 device_t pci_domain_dev;
37 struct resource *mem, *pref;
39 /* System error enable */
40 dword = pci_read_config32(dev, 0x04);
41 dword |= (1<<8); /* System error enable */
42 dword |= (1<<30); /* Clear possible errors */
43 pci_write_config32(dev, 0x04, dword);
47 word = pci_read_config16(dev, 0x48);
48 word |= (1<<0); /* MRL2MRM */
49 word |= (1<<2); /* MR2MRM */
50 pci_write_config16(dev, 0x48, word);
54 dword = pci_read_config32(dev, 0x4c);
55 dword |= 0x00440000; /*TABORT_SER_ENABLE Park Last Enable.*/
56 pci_write_config32(dev, 0x4c, dword);
59 pci_domain_dev = dev->bus->dev;
60 while (pci_domain_dev) {
61 if (pci_domain_dev->path.type == DEVICE_PATH_PCI_DOMAIN)
63 pci_domain_dev = pci_domain_dev->bus->dev;
67 return; /* Impossible */
69 pref = probe_resource(pci_domain_dev, IOINDEX_SUBTRACTIVE(2,0));
70 mem = probe_resource(pci_domain_dev, IOINDEX_SUBTRACTIVE(1,0));
73 return; /* Impossible */
75 if (!pref || pref->base > mem->base) {
76 dword = mem->base & (0xffff0000UL);
77 printk(BIOS_DEBUG, "PCI DOMAIN mem base = 0x%010Lx\n", mem->base);
79 dword = pref->base & (0xffff0000UL);
80 printk(BIOS_DEBUG, "PCI DOMAIN pref base = 0x%010Lx\n", pref->base);
83 printk(BIOS_DEBUG, "[0x50] <-- 0x%08x\n", dword);
84 pci_write_config32(dev, 0x50, dword); /* TOM */
87 static struct device_operations pci_ops = {
88 .read_resources = pci_bus_read_resources,
89 .set_resources = pci_dev_set_resources,
90 .enable_resources = pci_bus_enable_resources,
92 .scan_bus = pci_scan_bridge,
93 // .enable = mcp55_enable,
94 .reset_bus = pci_bus_reset,
97 static const struct pci_driver pci_driver __pci_driver = {
99 .vendor = PCI_VENDOR_ID_NVIDIA,
100 .device = PCI_DEVICE_ID_NVIDIA_MCP55_PCI,