src/southbridge/nvidia/mcp55/nic.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2004 Tyan Computer
   5  * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
   6  * Copyright (C) 2006,2007 AMD
   7  * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  22  */
  23
  24 #include <console/console.h>
  25 #include <device/device.h>
  26 #include <device/smbus.h>
  27 #include <device/pci.h>
  28 #include <device/pci_ids.h>
  29 #include <device/pci_ops.h>
  30 #include <arch/io.h>
  31 #include <delay.h>
  32 #include "mcp55.h"
  33
  34 static int phy_read(u32 base, unsigned phy_addr, unsigned phy_reg)
  35 {
  36         u32 dword;
  37         unsigned loop = 0x100;
  38         write32(base+0x190, 0x8000); //Clear MDIO lock bit
  39         mdelay(1);
  40         dword = read32(base+0x190);
  41         if(dword & (1<<15)) return -1;
  42
  43         write32(base+0x180, 1);
  44         write32(base + 0x190, (phy_addr<<5) | (phy_reg));
  45         do{
  46                 dword = read32(base + 0x190);
  47                 if(--loop==0) return -4;
  48         } while ((dword & (1<<15)) );
  49
  50         dword = read32(base + 0x180);
  51         if(dword & 1) return -3;
  52
  53         dword = read32(base + 0x194);
  54
  55         return dword;
  56
  57 }
  58
  59 static void phy_detect(u32 base)
  60 {
  61         u32 dword;
  62         int i;
  63         int val;
  64         unsigned id;
  65         dword = read32(base+0x188);
  66         dword &= ~(1<<20);
  67         write32(base+0x188, dword);
  68
  69         phy_read(base, 0, 1);
  70
  71         for(i=1; i<=32; i++) {
  72                 int phyaddr = i & 0x1f;
  73                 val = phy_read(base, phyaddr, 1);
  74                 if(val<0) continue;
  75                 if((val & 0xffff) == 0xfffff) continue;
  76                 if((val & 0xffff) == 0) continue;
  77                 if(!(val & 1)) {
  78                         break; // Ethernet PHY
  79                 }
  80                 val = phy_read(base, phyaddr, 3);
  81                 if (val < 0 || val == 0xffff) continue;
  82                 id = val & 0xfc00;
  83                 val = phy_read(base, phyaddr, 2);
  84                 if (val < 0 || val == 0xffff) continue;
  85                 id |= ((val & 0xffff)<<16);
  86                 printk(BIOS_DEBUG, "MCP55 MAC PHY ID 0x%08x PHY ADDR %d\n", id, i);
  87 //              if((id == 0xe0180000) || (id==0x0032cc00))
  88                         break;
  89         }
  90
  91         if(i>32) {
  92                 printk(BIOS_DEBUG, "MCP55 MAC PHY not found\n");
  93         }
  94 }
  95
  96 static void nic_init(struct device *dev)
  97 {
  98         u32 mac_h, mac_l;
  99         int eeprom_valid = 0;
 100         struct southbridge_nvidia_mcp55_config *conf;
 101
 102         static u32 nic_index = 0;
 103
 104         u32 base;
 105         struct resource *res;
 106
 107         res = find_resource(dev, 0x10);
 108
 109         if(!res) return;
 110
 111         base = res->base;
 112
 113         phy_detect(base);
 114
 115 #define NvRegPhyInterface       0xC0
 116 #define PHY_RGMII       0x10000000
 117
 118         write32(base + NvRegPhyInterface, PHY_RGMII);
 119
 120         conf = dev->chip_info;
 121
 122         if(conf->mac_eeprom_smbus != 0) {
 123 //      read MAC address from EEPROM at first
 124                 struct device *dev_eeprom;
 125                 dev_eeprom = dev_find_slot_on_smbus(conf->mac_eeprom_smbus, conf->mac_eeprom_addr);
 126
 127                 if(dev_eeprom) {
 128                 //      if that is valid we will use that
 129                         unsigned char dat[6];
 130                         int status;
 131                         int i;
 132                         for(i=0;i<6;i++) {
 133                                 status = smbus_read_byte(dev_eeprom, i);
 134                                 if(status < 0) break;
 135                                 dat[i] = status & 0xff;
 136                         }
 137                         if(status >= 0) {
 138                                 mac_l = 0;
 139                                 for(i=3;i>=0;i--) {
 140                                         mac_l <<= 8;
 141                                         mac_l += dat[i];
 142                                 }
 143                                 if(mac_l != 0xffffffff) {
 144                                         mac_l += nic_index;
 145                                         mac_h = 0;
 146                                         for(i=5;i>=4;i--) {
 147                                                 mac_h <<= 8;
 148                                                 mac_h += dat[i];
 149                                         }
 150                                         eeprom_valid = 1;
 151                                 }
 152                         }
 153                 }
 154         }
 155 //      if that is invalid we will read that from romstrap
 156         if(!eeprom_valid) {
 157                 unsigned long mac_pos;
 158                 mac_pos = 0xffffffd0; // refer to romstrap.inc and romstrap.lds
 159                 mac_l = read32(mac_pos) + nic_index; // overflow?
 160                 mac_h = read32(mac_pos + 4);
 161
 162         }
 163 #if 1
 164 //      set that into NIC MMIO
 165 #define NvRegMacAddrA   0xA8
 166 #define NvRegMacAddrB   0xAC
 167         write32(base + NvRegMacAddrA, mac_l);
 168         write32(base + NvRegMacAddrB, mac_h);
 169 #else
 170 //      set that into NIC
 171         pci_write_config32(dev, 0xa8, mac_l);
 172         pci_write_config32(dev, 0xac, mac_h);
 173 #endif
 174
 175         nic_index++;
 176
 177 #if CONFIG_PCI_ROM_RUN == 1
 178         pci_dev_init(dev);// it will init option rom
 179 #endif
 180
 181 }
 182
 183 static struct device_operations nic_ops  = {
 184         .read_resources = pci_dev_read_resources,
 185         .set_resources  = pci_dev_set_resources,
 186         .enable_resources       = pci_dev_enable_resources,
 187         .init           = nic_init,
 188         .scan_bus       = 0,
 189 //      .enable         = mcp55_enable,
 190         .ops_pci        = &mcp55_pci_ops,
 191 };
 192 static const struct pci_driver nic_driver __pci_driver = {
 193         .ops    = &nic_ops,
 194         .vendor = PCI_VENDOR_ID_NVIDIA,
 195         .device = PCI_DEVICE_ID_NVIDIA_MCP55_NIC,
 196 };
 197 static const struct pci_driver nic_bridge_driver __pci_driver = {
 198         .ops    = &nic_ops,
 199         .vendor = PCI_VENDOR_ID_NVIDIA,
 200         .device = PCI_DEVICE_ID_NVIDIA_MCP55_NIC_BRIDGE,
 201 };