src/southbridge/nvidia/mcp55/mcp55_lpc.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2003 Linux Networx
   5  * Copyright (C) 2003 SuSE Linux AG
   6  * Copyright (C) 2004 Tyan Computer
   7  * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
   8  * Copyright (C) 2006,2007 AMD
   9  * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  24  */
  25
  26 #include <console/console.h>
  27 #include <device/device.h>
  28 #include <device/pci.h>
  29 #include <device/pnp.h>
  30 #include <device/pci_ids.h>
  31 #include <device/pci_ops.h>
  32 #include <pc80/mc146818rtc.h>
  33 #include <pc80/isa-dma.h>
  34 #include <bitops.h>
  35 #include <arch/io.h>
  36 #include <cpu/x86/lapic.h>
  37 #include <stdlib.h>
  38 #include "mcp55.h"
  39
  40 #define NMI_OFF 0
  41
  42 struct ioapicreg {
  43         unsigned int reg;
  44         unsigned int value_low, value_high;
  45 };
  46
  47 static struct ioapicreg ioapicregvalues[] = {
  48 #define ALL             (0xff << 24)
  49 #define NONE            (0)
  50 #define DISABLED        (1 << 16)
  51 #define ENABLED         (0 << 16)
  52 #define TRIGGER_EDGE    (0 << 15)
  53 #define TRIGGER_LEVEL   (1 << 15)
  54 #define POLARITY_HIGH   (0 << 13)
  55 #define POLARITY_LOW    (1 << 13)
  56 #define PHYSICAL_DEST   (0 << 11)
  57 #define LOGICAL_DEST    (1 << 11)
  58 #define ExtINT          (7 << 8)
  59 #define NMI             (4 << 8)
  60 #define SMI             (2 << 8)
  61 #define INT             (1 << 8)
  62         /* IO-APIC virtual wire mode configuration */
  63         /* mask, trigger, polarity, destination, delivery, vector */
  64         {   0, ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT, NONE},
  65         {   1, DISABLED, NONE},
  66         {   2, DISABLED, NONE},
  67         {   3, DISABLED, NONE},
  68         {   4, DISABLED, NONE},
  69         {   5, DISABLED, NONE},
  70         {   6, DISABLED, NONE},
  71         {   7, DISABLED, NONE},
  72         {   8, DISABLED, NONE},
  73         {   9, DISABLED, NONE},
  74         {  10, DISABLED, NONE},
  75         {  11, DISABLED, NONE},
  76         {  12, DISABLED, NONE},
  77         {  13, DISABLED, NONE},
  78         {  14, DISABLED, NONE},
  79         {  15, DISABLED, NONE},
  80         {  16, DISABLED, NONE},
  81         {  17, DISABLED, NONE},
  82         {  18, DISABLED, NONE},
  83         {  19, DISABLED, NONE},
  84         {  20, DISABLED, NONE},
  85         {  21, DISABLED, NONE},
  86         {  22, DISABLED, NONE},
  87         {  23, DISABLED, NONE},
  88         /* Be careful and don't write past the end... */
  89 };
  90
  91 static void setup_ioapic(unsigned long ioapic_base, int master)
  92 {
  93         int i;
  94         unsigned long value_low, value_high;
  95 //      unsigned long ioapic_base = 0xfec00000;
  96         volatile unsigned long *l;
  97         struct ioapicreg *a = ioapicregvalues;
  98
  99         if (master) {
 100                 ioapicregvalues[0].value_high = lapicid()<<(56-32);
 101                 ioapicregvalues[0].value_low = ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT;
 102         }
 103         else {
 104                 ioapicregvalues[0].value_high = NONE;
 105                 ioapicregvalues[0].value_low = DISABLED;
 106         }
 107
 108         l = (unsigned long *) ioapic_base;
 109
 110         for (i = 0; i < ARRAY_SIZE(ioapicregvalues);
 111              i++, a++) {
 112                 l[0] = (a->reg * 2) + 0x10;
 113                 l[4] = a->value_low;
 114                 value_low = l[4];
 115                 l[0] = (a->reg *2) + 0x11;
 116                 l[4] = a->value_high;
 117                 value_high = l[4];
 118                 if ((i==0) && (value_low == 0xffffffff)) {
 119                         printk_warning("IO APIC not responding.\n");
 120                         return;
 121                 }
 122                 printk_spew("for IRQ, reg 0x%08x value 0x%08x 0x%08x\n",
 123                             a->reg, a->value_low, a->value_high);
 124         }
 125 }
 126
 127 // 0x7a or e3
 128 #define PREVIOUS_POWER_STATE    0x7A
 129
 130 #define MAINBOARD_POWER_OFF     0
 131 #define MAINBOARD_POWER_ON      1
 132 #define SLOW_CPU_OFF            0
 133 #define SLOW_CPU__ON            1
 134
 135 #ifndef MAINBOARD_POWER_ON_AFTER_POWER_FAIL
 136 #define MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
 137 #endif
 138
 139 static void lpc_common_init(device_t dev, int master)
 140 {
 141         uint8_t byte;
 142         uint32_t dword;
 143
 144         /* IO APIC initialization */
 145         byte = pci_read_config8(dev, 0x74);
 146         byte |= (1<<0); // enable APIC
 147         pci_write_config8(dev, 0x74, byte);
 148         dword = pci_read_config32(dev, PCI_BASE_ADDRESS_1); // 0x14
 149
 150         setup_ioapic(dword, master);
 151 }
 152
 153 static void lpc_slave_init(device_t dev)
 154 {
 155         lpc_common_init(dev, 0);
 156 }
 157
 158 #if 0
 159 static void enable_hpet(struct device *dev)
 160 {
 161         unsigned long hpet_address;
 162
 163         pci_write_config32(dev,0x44, 0xfed00001);
 164         hpet_address=pci_read_config32(dev,0x44)& 0xfffffffe;
 165         printk_debug("enabling HPET @0x%x\n", hpet_address);
 166 }
 167 #endif
 168
 169 static void lpc_init(device_t dev)
 170 {
 171         uint8_t byte;
 172         uint8_t byte_old;
 173         uint32_t on;
 174         uint32_t nmi_option;
 175
 176         lpc_common_init(dev, 1);
 177
 178 #if 0
 179         /* posted memory write enable */
 180         byte = pci_read_config8(dev, 0x46);
 181         pci_write_config8(dev, 0x46, byte | (1<<0));
 182 #endif
 183         /* power after power fail */
 184
 185 #if 1
 186         on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
 187         get_option("power_on_after_fail", &on);
 188         byte = pci_read_config8(dev, PREVIOUS_POWER_STATE);
 189         byte &= ~0x40;
 190         if (!on) {
 191                 byte |= 0x40;
 192         }
 193         pci_write_config8(dev, PREVIOUS_POWER_STATE, byte);
 194         printk_info("set power %s after power fail\n", on?"on":"off");
 195 #endif
 196         /* Throttle the CPU speed down for testing */
 197         on = SLOW_CPU_OFF;
 198         get_option("slow_cpu", &on);
 199         if(on) {
 200                 uint16_t pm10_bar;
 201                 uint32_t dword;
 202                 pm10_bar = (pci_read_config16(dev, 0x60)&0xff00);
 203                 outl(((on<<1)+0x10)  ,(pm10_bar + 0x10));
 204                 dword = inl(pm10_bar + 0x10);
 205                 on = 8-on;
 206                 printk_debug("Throttling CPU %2d.%1.1d percent.\n",
 207                              (on*12)+(on>>1),(on&1)*5);
 208         }
 209
 210 #if 0
 211 // default is enabled
 212         /* Enable Port 92 fast reset */
 213         byte = pci_read_config8(dev, 0xe8);
 214         byte |= ~(1 << 3);
 215         pci_write_config8(dev, 0xe8, byte);
 216 #endif
 217
 218         /* Enable Error reporting */
 219         /* Set up sync flood detected */
 220         byte = pci_read_config8(dev, 0x47);
 221         byte |= (1 << 1);
 222         pci_write_config8(dev, 0x47, byte);
 223
 224         /* Set up NMI on errors */
 225         byte = inb(0x70); // RTC70
 226         byte_old = byte;
 227         nmi_option = NMI_OFF;
 228         get_option("nmi", &nmi_option);
 229         if (nmi_option) {
 230                 byte &= ~(1 << 7); /* set NMI */
 231         } else {
 232                 byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW
 233         }
 234         if( byte != byte_old) {
 235                 outb(0x70, byte);
 236         }
 237
 238         /* Initialize the real time clock */
 239         rtc_init(0);
 240
 241         /* Initialize isa dma */
 242         isa_dma_init();
 243
 244         /* Initialize the High Precision Event Timers */
 245 //      enable_hpet(dev);
 246
 247 }
 248
 249 static void mcp55_lpc_read_resources(device_t dev)
 250 {
 251         struct resource *res;
 252
 253         /* Get the normal pci resources of this device */
 254         pci_dev_read_resources(dev); // We got one for APIC, or one more for TRAP
 255
 256         /* Add an extra subtractive resource for both memory and I/O */
 257         res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
 258         res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
 259
 260         res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
 261         res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
 262
 263 }
 264
 265 /**
 266  * @brief Enable resources for children devices
 267  *
 268  * @param dev the device whos children's resources are to be enabled
 269  *
 270  * This function is call by the global enable_resources() indirectly via the
 271  * device_operation::enable_resources() method of devices.
 272  *
 273  * Indirect mutual recursion:
 274  *      enable_childrens_resources() -> enable_resources()
 275  *      enable_resources() -> device_operation::enable_resources()
 276  *      device_operation::enable_resources() -> enable_children_resources()
 277  */
 278 static void mcp55_lpc_enable_childrens_resources(device_t dev)
 279 {
 280         unsigned link;
 281         uint32_t reg, reg_var[4];
 282         int i;
 283         int var_num = 0;
 284
 285         reg = pci_read_config32(dev, 0xa0);
 286
 287         for (link = 0; link < dev->links; link++) {
 288                 device_t child;
 289                 for (child = dev->link[link].children; child; child = child->sibling) {
 290                         enable_resources(child);
 291                         if(child->have_resources && (child->path.type == DEVICE_PATH_PNP)) {
 292                                 for(i=0;i<child->resources;i++) {
 293                                         struct resource *res;
 294                                         unsigned long base, end; // don't need long long
 295                                         res = &child->resource[i];
 296                                         if(!(res->flags & IORESOURCE_IO)) continue;
 297                                         base = res->base;
 298                                         end = resource_end(res);
 299                                         printk_debug("mcp55 lpc decode:%s, base=0x%08x, end=0x%08x\n",dev_path(child),base, end);
 300                                         switch(base) {
 301                                         case 0x3f8: // COM1
 302                                                 reg |= (1<<0);  break;
 303                                         case 0x2f8: // COM2
 304                                                 reg |= (1<<1);  break;
 305                                         case 0x378: // Parallal 1
 306                                                 reg |= (1<<24); break;
 307                                         case 0x3f0: // FD0
 308                                                 reg |= (1<<20); break;
 309                                         case 0x220:  // Aduio 0
 310                                                 reg |= (1<<8);  break;
 311                                         case 0x300:  // Midi 0
 312                                                 reg |= (1<<12); break;
 313                                         }
 314                                         if( (base == 0x290) || (base >= 0x400)) {
 315                                                 if(var_num>=4) continue; // only 4 var ; compact them ?
 316                                                 reg |= (1<<(28+var_num));
 317                                                 reg_var[var_num++] = (base & 0xffff)|((end & 0xffff)<<16);
 318                                         }
 319                                 }
 320                         }
 321                 }
 322         }
 323         pci_write_config32(dev, 0xa0, reg);
 324         for(i=0;i<var_num;i++) {
 325                 pci_write_config32(dev, 0xa8 + i*4, reg_var[i]);
 326         }
 327
 328
 329 }
 330
 331 static void mcp55_lpc_enable_resources(device_t dev)
 332 {
 333         pci_dev_enable_resources(dev);
 334         mcp55_lpc_enable_childrens_resources(dev);
 335 }
 336
 337 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 338 {
 339         pci_write_config32(dev, 0x40,
 340                 ((device & 0xffff) << 16) | (vendor & 0xffff));
 341 }
 342
 343 static struct pci_operations lops_pci = {
 344         .set_subsystem  = lpci_set_subsystem,
 345 };
 346
 347 static struct device_operations lpc_ops  = {
 348         .read_resources = mcp55_lpc_read_resources,
 349         .set_resources  = pci_dev_set_resources,
 350         .enable_resources       = mcp55_lpc_enable_resources,
 351         .init           = lpc_init,
 352         .scan_bus       = scan_static_bus,
 353 //      .enable         = mcp55_enable,
 354         .ops_pci        = &lops_pci,
 355 };
 356 static const struct pci_driver lpc_driver __pci_driver = {
 357         .ops    = &lpc_ops,
 358         .vendor = PCI_VENDOR_ID_NVIDIA,
 359         .device = PCI_DEVICE_ID_NVIDIA_MCP55_LPC,
 360 };
 361
 362 static const struct pci_driver lpc_driver_pro __pci_driver = {
 363         .ops    = &lpc_ops,
 364         .vendor = PCI_VENDOR_ID_NVIDIA,
 365         .device = PCI_DEVICE_ID_NVIDIA_MCP55_PRO,
 366 };
 367
 368 static const struct pci_driver lpc_driver_lpc2 __pci_driver = {
 369         .ops    = &lpc_ops,
 370         .vendor = PCI_VENDOR_ID_NVIDIA,
 371         .device = PCI_DEVICE_ID_NVIDIA_MCP55_LPC_2,
 372 };
 373 static const struct pci_driver lpc_driver_lpc3 __pci_driver = {
 374         .ops    = &lpc_ops,
 375         .vendor = PCI_VENDOR_ID_NVIDIA,
 376         .device = PCI_DEVICE_ID_NVIDIA_MCP55_LPC_3,
 377 };
 378 static const struct pci_driver lpc_driver_lpc4 __pci_driver = {
 379         .ops    = &lpc_ops,
 380         .vendor = PCI_VENDOR_ID_NVIDIA,
 381         .device = PCI_DEVICE_ID_NVIDIA_MCP55_LPC_4,
 382 };
 383 static const struct pci_driver lpc_driver_lpc5 __pci_driver = {
 384         .ops    = &lpc_ops,
 385         .vendor = PCI_VENDOR_ID_NVIDIA,
 386         .device = PCI_DEVICE_ID_NVIDIA_MCP55_LPC_5,
 387 };
 388 static const struct pci_driver lpc_driver_lpc6 __pci_driver = {
 389         .ops    = &lpc_ops,
 390         .vendor = PCI_VENDOR_ID_NVIDIA,
 391         .device = PCI_DEVICE_ID_NVIDIA_MCP55_LPC_6,
 392 };
 393
 394 static struct device_operations lpc_slave_ops  = {
 395         .read_resources = mcp55_lpc_read_resources,
 396         .set_resources  = pci_dev_set_resources,
 397         .enable_resources       = pci_dev_enable_resources,
 398         .init           = lpc_slave_init,
 399 //      .enable         = mcp55_enable,
 400         .ops_pci        = &lops_pci,
 401 };
 402
 403 static const struct pci_driver lpc_driver_slave __pci_driver = {
 404         .ops    = &lpc_slave_ops,
 405         .vendor = PCI_VENDOR_ID_NVIDIA,
 406         .device = PCI_DEVICE_ID_NVIDIA_MCP55_SLAVE,
 407 };