2 * This file is part of the coreboot project.
4 * Copyright (C) 2003 Linux Networx
5 * Copyright (C) 2003 SuSE Linux AG
6 * Copyright (C) 2004 Tyan Computer
7 * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
8 * Copyright (C) 2006,2007 AMD
9 * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
26 #include <console/console.h>
27 #include <device/device.h>
28 #include <device/pci.h>
29 #include <device/pnp.h>
30 #include <device/pci_ids.h>
31 #include <device/pci_ops.h>
32 #include <pc80/mc146818rtc.h>
33 #include <pc80/isa-dma.h>
36 #include <cpu/x86/lapic.h>
44 unsigned int value_low, value_high;
47 static struct ioapicreg ioapicregvalues[] = {
48 #define ALL (0xff << 24)
50 #define DISABLED (1 << 16)
51 #define ENABLED (0 << 16)
52 #define TRIGGER_EDGE (0 << 15)
53 #define TRIGGER_LEVEL (1 << 15)
54 #define POLARITY_HIGH (0 << 13)
55 #define POLARITY_LOW (1 << 13)
56 #define PHYSICAL_DEST (0 << 11)
57 #define LOGICAL_DEST (1 << 11)
58 #define ExtINT (7 << 8)
62 /* IO-APIC virtual wire mode configuration */
63 /* mask, trigger, polarity, destination, delivery, vector */
64 { 0, ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT, NONE},
74 { 10, DISABLED, NONE},
75 { 11, DISABLED, NONE},
76 { 12, DISABLED, NONE},
77 { 13, DISABLED, NONE},
78 { 14, DISABLED, NONE},
79 { 15, DISABLED, NONE},
80 { 16, DISABLED, NONE},
81 { 17, DISABLED, NONE},
82 { 18, DISABLED, NONE},
83 { 19, DISABLED, NONE},
84 { 20, DISABLED, NONE},
85 { 21, DISABLED, NONE},
86 { 22, DISABLED, NONE},
87 { 23, DISABLED, NONE},
88 /* Be careful and don't write past the end... */
91 static void setup_ioapic(unsigned long ioapic_base, int master)
94 unsigned long value_low, value_high;
95 // unsigned long ioapic_base = 0xfec00000;
96 volatile unsigned long *l;
97 struct ioapicreg *a = ioapicregvalues;
100 ioapicregvalues[0].value_high = lapicid()<<(56-32);
101 ioapicregvalues[0].value_low = ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT;
104 ioapicregvalues[0].value_high = NONE;
105 ioapicregvalues[0].value_low = DISABLED;
108 l = (unsigned long *) ioapic_base;
110 for (i = 0; i < ARRAY_SIZE(ioapicregvalues);
112 l[0] = (a->reg * 2) + 0x10;
115 l[0] = (a->reg *2) + 0x11;
116 l[4] = a->value_high;
118 if ((i==0) && (value_low == 0xffffffff)) {
119 printk_warning("IO APIC not responding.\n");
122 printk_spew("for IRQ, reg 0x%08x value 0x%08x 0x%08x\n",
123 a->reg, a->value_low, a->value_high);
128 #define PREVIOUS_POWER_STATE 0x7A
130 #define MAINBOARD_POWER_OFF 0
131 #define MAINBOARD_POWER_ON 1
132 #define SLOW_CPU_OFF 0
133 #define SLOW_CPU__ON 1
135 #ifndef MAINBOARD_POWER_ON_AFTER_POWER_FAIL
136 #define MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
139 static void lpc_common_init(device_t dev, int master)
144 /* IO APIC initialization */
145 byte = pci_read_config8(dev, 0x74);
146 byte |= (1<<0); // enable APIC
147 pci_write_config8(dev, 0x74, byte);
148 dword = pci_read_config32(dev, PCI_BASE_ADDRESS_1); // 0x14
150 setup_ioapic(dword, master);
153 static void lpc_slave_init(device_t dev)
155 lpc_common_init(dev, 0);
158 static void enable_hpet(struct device *dev)
160 unsigned long hpet_address;
162 pci_write_config32(dev,0x44, 0xfed00001);
163 hpet_address=pci_read_config32(dev,0x44)& 0xfffffffe;
164 printk_debug("enabling HPET @0x%x\n", hpet_address);
167 static void lpc_init(device_t dev)
174 lpc_common_init(dev, 1);
177 /* posted memory write enable */
178 byte = pci_read_config8(dev, 0x46);
179 pci_write_config8(dev, 0x46, byte | (1<<0));
181 /* power after power fail */
184 on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
185 get_option(&on, "power_on_after_fail");
186 byte = pci_read_config8(dev, PREVIOUS_POWER_STATE);
191 pci_write_config8(dev, PREVIOUS_POWER_STATE, byte);
192 printk_info("set power %s after power fail\n", on?"on":"off");
194 /* Throttle the CPU speed down for testing */
196 get_option(&on, "slow_cpu");
200 pm10_bar = (pci_read_config16(dev, 0x60)&0xff00);
201 outl(((on<<1)+0x10) ,(pm10_bar + 0x10));
202 dword = inl(pm10_bar + 0x10);
204 printk_debug("Throttling CPU %2d.%1.1d percent.\n",
205 (on*12)+(on>>1),(on&1)*5);
209 // default is enabled
210 /* Enable Port 92 fast reset */
211 byte = pci_read_config8(dev, 0xe8);
213 pci_write_config8(dev, 0xe8, byte);
216 /* Enable Error reporting */
217 /* Set up sync flood detected */
218 byte = pci_read_config8(dev, 0x47);
220 pci_write_config8(dev, 0x47, byte);
222 /* Set up NMI on errors */
223 byte = inb(0x70); // RTC70
225 nmi_option = NMI_OFF;
226 get_option(&nmi_option, "nmi");
228 byte &= ~(1 << 7); /* set NMI */
230 byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW
232 if( byte != byte_old) {
236 /* Initialize the real time clock */
239 /* Initialize isa dma */
242 /* Initialize the High Precision Event Timers */
247 static void mcp55_lpc_read_resources(device_t dev)
249 struct resource *res;
251 /* Get the normal pci resources of this device */
252 pci_dev_read_resources(dev); // We got one for APIC, or one more for TRAP
254 /* Add an extra subtractive resource for both memory and I/O */
255 res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
256 res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
258 res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
259 res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
264 * @brief Enable resources for children devices
266 * @param dev the device whos children's resources are to be enabled
268 * This function is call by the global enable_resources() indirectly via the
269 * device_operation::enable_resources() method of devices.
271 * Indirect mutual recursion:
272 * enable_childrens_resources() -> enable_resources()
273 * enable_resources() -> device_operation::enable_resources()
274 * device_operation::enable_resources() -> enable_children_resources()
276 static void mcp55_lpc_enable_childrens_resources(device_t dev)
279 uint32_t reg, reg_var[4];
283 reg = pci_read_config32(dev, 0xa0);
285 for (link = 0; link < dev->links; link++) {
287 for (child = dev->link[link].children; child; child = child->sibling) {
288 enable_resources(child);
289 if(child->have_resources && (child->path.type == DEVICE_PATH_PNP)) {
290 for(i=0;i<child->resources;i++) {
291 struct resource *res;
292 unsigned long base, end; // don't need long long
293 res = &child->resource[i];
294 if(!(res->flags & IORESOURCE_IO)) continue;
296 end = resource_end(res);
297 printk_debug("mcp55 lpc decode:%s, base=0x%08x, end=0x%08x\n",dev_path(child),base, end);
300 reg |= (1<<0); break;
302 reg |= (1<<1); break;
303 case 0x378: // Parallal 1
304 reg |= (1<<24); break;
306 reg |= (1<<20); break;
307 case 0x220: // Aduio 0
308 reg |= (1<<8); break;
309 case 0x300: // Midi 0
310 reg |= (1<<12); break;
312 if( (base == 0x290) || (base >= 0x400)) {
313 if(var_num>=4) continue; // only 4 var ; compact them ?
314 reg |= (1<<(28+var_num));
315 reg_var[var_num++] = (base & 0xffff)|((end & 0xffff)<<16);
321 pci_write_config32(dev, 0xa0, reg);
322 for(i=0;i<var_num;i++) {
323 pci_write_config32(dev, 0xa8 + i*4, reg_var[i]);
329 static void mcp55_lpc_enable_resources(device_t dev)
331 pci_dev_enable_resources(dev);
332 mcp55_lpc_enable_childrens_resources(dev);
335 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
337 pci_write_config32(dev, 0x40,
338 ((device & 0xffff) << 16) | (vendor & 0xffff));
341 static struct pci_operations lops_pci = {
342 .set_subsystem = lpci_set_subsystem,
345 static struct device_operations lpc_ops = {
346 .read_resources = mcp55_lpc_read_resources,
347 .set_resources = pci_dev_set_resources,
348 .enable_resources = mcp55_lpc_enable_resources,
350 .scan_bus = scan_static_bus,
351 // .enable = mcp55_enable,
352 .ops_pci = &lops_pci,
354 static const struct pci_driver lpc_driver __pci_driver = {
356 .vendor = PCI_VENDOR_ID_NVIDIA,
357 .device = PCI_DEVICE_ID_NVIDIA_MCP55_LPC,
360 static const struct pci_driver lpc_driver_pro __pci_driver = {
362 .vendor = PCI_VENDOR_ID_NVIDIA,
363 .device = PCI_DEVICE_ID_NVIDIA_MCP55_PRO,
366 static const struct pci_driver lpc_driver_lpc2 __pci_driver = {
368 .vendor = PCI_VENDOR_ID_NVIDIA,
369 .device = PCI_DEVICE_ID_NVIDIA_MCP55_LPC_2,
371 static const struct pci_driver lpc_driver_lpc3 __pci_driver = {
373 .vendor = PCI_VENDOR_ID_NVIDIA,
374 .device = PCI_DEVICE_ID_NVIDIA_MCP55_LPC_3,
376 static const struct pci_driver lpc_driver_lpc4 __pci_driver = {
378 .vendor = PCI_VENDOR_ID_NVIDIA,
379 .device = PCI_DEVICE_ID_NVIDIA_MCP55_LPC_4,
381 static const struct pci_driver lpc_driver_lpc5 __pci_driver = {
383 .vendor = PCI_VENDOR_ID_NVIDIA,
384 .device = PCI_DEVICE_ID_NVIDIA_MCP55_LPC_5,
386 static const struct pci_driver lpc_driver_lpc6 __pci_driver = {
388 .vendor = PCI_VENDOR_ID_NVIDIA,
389 .device = PCI_DEVICE_ID_NVIDIA_MCP55_LPC_6,
392 static struct device_operations lpc_slave_ops = {
393 .read_resources = mcp55_lpc_read_resources,
394 .set_resources = pci_dev_set_resources,
395 .enable_resources = pci_dev_enable_resources,
396 .init = lpc_slave_init,
397 // .enable = mcp55_enable,
398 .ops_pci = &lops_pci,
401 static const struct pci_driver lpc_driver_slave __pci_driver = {
402 .ops = &lpc_slave_ops,
403 .vendor = PCI_VENDOR_ID_NVIDIA,
404 .device = PCI_DEVICE_ID_NVIDIA_MCP55_SLAVE,