src/southbridge/nvidia/mcp55/mcp55_lpc.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2003 Linux Networx
   5  * Copyright (C) 2003 SuSE Linux AG
   6  * Copyright (C) 2004 Tyan Computer
   7  * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
   8  * Copyright (C) 2006,2007 AMD
   9  * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  24  */
  25
  26 #include <console/console.h>
  27 #include <device/device.h>
  28 #include <device/pci.h>
  29 #include <device/pnp.h>
  30 #include <device/pci_ids.h>
  31 #include <device/pci_ops.h>
  32 #include <pc80/mc146818rtc.h>
  33 #include <pc80/isa-dma.h>
  34 #include <bitops.h>
  35 #include <arch/io.h>
  36 #include <arch/ioapic.h>
  37 #include <cpu/x86/lapic.h>
  38 #include <stdlib.h>
  39 #include "mcp55.h"
  40
  41 #define NMI_OFF 0
  42
  43 // 0x7a or e3
  44 #define PREVIOUS_POWER_STATE    0x7A
  45
  46 #define MAINBOARD_POWER_OFF     0
  47 #define MAINBOARD_POWER_ON      1
  48 #define SLOW_CPU_OFF            0
  49 #define SLOW_CPU__ON            1
  50
  51 #ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
  52 #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
  53 #endif
  54
  55 static void lpc_common_init(device_t dev, int master)
  56 {
  57         uint8_t byte;
  58         uint32_t ioapic_base;
  59
  60         /* IO APIC initialization */
  61         byte = pci_read_config8(dev, 0x74);
  62         byte |= (1<<0); // enable APIC
  63         pci_write_config8(dev, 0x74, byte);
  64         ioapic_base = pci_read_config32(dev, PCI_BASE_ADDRESS_1); // 0x14
  65
  66         if (master)
  67                 setup_ioapic(ioapic_base, 0);
  68         else
  69                 clear_ioapic(ioapic_base);
  70 }
  71
  72 static void lpc_slave_init(device_t dev)
  73 {
  74         lpc_common_init(dev, 0);
  75 }
  76
  77 static void enable_hpet(struct device *dev)
  78 {
  79         unsigned long hpet_address;
  80
  81         pci_write_config32(dev,0x44, 0xfed00001);
  82         hpet_address=pci_read_config32(dev,0x44)& 0xfffffffe;
  83         printk(BIOS_DEBUG, "enabling HPET @0x%lx\n", hpet_address);
  84 }
  85
  86 static void lpc_init(device_t dev)
  87 {
  88         uint8_t byte;
  89         uint8_t byte_old;
  90         int on;
  91         int nmi_option;
  92
  93         lpc_common_init(dev, 1);
  94
  95 #if 0
  96         /* posted memory write enable */
  97         byte = pci_read_config8(dev, 0x46);
  98         pci_write_config8(dev, 0x46, byte | (1<<0));
  99 #endif
 100         /* power after power fail */
 101
 102 #if 1
 103         on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
 104         get_option(&on, "power_on_after_fail");
 105         byte = pci_read_config8(dev, PREVIOUS_POWER_STATE);
 106         byte &= ~0x40;
 107         if (!on) {
 108                 byte |= 0x40;
 109         }
 110         pci_write_config8(dev, PREVIOUS_POWER_STATE, byte);
 111         printk(BIOS_INFO, "set power %s after power fail\n", on?"on":"off");
 112 #endif
 113         /* Throttle the CPU speed down for testing */
 114         on = SLOW_CPU_OFF;
 115         get_option(&on, "slow_cpu");
 116         if(on) {
 117                 uint16_t pm10_bar;
 118                 uint32_t dword;
 119                 pm10_bar = (pci_read_config16(dev, 0x60)&0xff00);
 120                 outl(((on<<1)+0x10)  ,(pm10_bar + 0x10));
 121                 dword = inl(pm10_bar + 0x10);
 122                 on = 8-on;
 123                 printk(BIOS_DEBUG, "Throttling CPU %2d.%1.1d percent.\n",
 124                              (on*12)+(on>>1),(on&1)*5);
 125         }
 126
 127 #if 0
 128 // default is enabled
 129         /* Enable Port 92 fast reset */
 130         byte = pci_read_config8(dev, 0xe8);
 131         byte |= ~(1 << 3);
 132         pci_write_config8(dev, 0xe8, byte);
 133 #endif
 134
 135         /* Enable Error reporting */
 136         /* Set up sync flood detected */
 137         byte = pci_read_config8(dev, 0x47);
 138         byte |= (1 << 1);
 139         pci_write_config8(dev, 0x47, byte);
 140
 141         /* Set up NMI on errors */
 142         byte = inb(0x70); // RTC70
 143         byte_old = byte;
 144         nmi_option = NMI_OFF;
 145         get_option(&nmi_option, "nmi");
 146         if (nmi_option) {
 147                 byte &= ~(1 << 7); /* set NMI */
 148         } else {
 149                 byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW
 150         }
 151         if( byte != byte_old) {
 152                 outb(byte, 0x70);
 153         }
 154
 155         /* Initialize the real time clock */
 156         rtc_init(0);
 157
 158         /* Initialize isa dma */
 159         isa_dma_init();
 160
 161         /* Initialize the High Precision Event Timers */
 162         enable_hpet(dev);
 163
 164 }
 165
 166 static void mcp55_lpc_read_resources(device_t dev)
 167 {
 168         struct resource *res;
 169
 170         /* Get the normal PCI resources of this device. */
 171         /* We got one for APIC, or one more for TRAP. */
 172         pci_dev_read_resources(dev);
 173
 174         /* Add an extra subtractive resource for both memory and I/O. */
 175         res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
 176         res->base = 0;
 177         res->size = 0x1000;
 178         res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
 179                      IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 180
 181         res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
 182         res->base = 0xff800000;
 183         res->size = 0x00800000; /* 8 MB for flash */
 184         res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
 185                      IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 186
 187         res = new_resource(dev, 3); /* IOAPIC */
 188         res->base = 0xfec00000;
 189         res->size = 0x00001000;
 190         res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 191 }
 192
 193 /**
 194  * @brief Enable resources for children devices
 195  *
 196  * @param dev the device whos children's resources are to be enabled
 197  *
 198  * This function is called by the global enable_resources() indirectly via the
 199  * device_operation::enable_resources() method of devices.
 200  *
 201  * Indirect mutual recursion:
 202  *      enable_childrens_resources() -> enable_resources()
 203  *      enable_resources() -> device_operation::enable_resources()
 204  *      device_operation::enable_resources() -> enable_children_resources()
 205  */
 206 static void mcp55_lpc_enable_childrens_resources(device_t dev)
 207 {
 208         unsigned link;
 209         uint32_t reg, reg_var[4];
 210         int i;
 211         int var_num = 0;
 212
 213         reg = pci_read_config32(dev, 0xa0);
 214
 215         for (link = 0; link < dev->links; link++) {
 216                 device_t child;
 217                 for (child = dev->link[link].children; child; child = child->sibling) {
 218                         enable_resources(child);
 219                         if(child->enabled && (child->path.type == DEVICE_PATH_PNP)) {
 220                                 for(i=0;i<child->resources;i++) {
 221                                         struct resource *res;
 222                                         unsigned long base, end; // don't need long long
 223                                         res = &child->resource[i];
 224                                         if(!(res->flags & IORESOURCE_IO)) continue;
 225                                         base = res->base;
 226                                         end = resource_end(res);
 227                                         printk(BIOS_DEBUG, "mcp55 lpc decode:%s, base=0x%08lx, end=0x%08lx\n",dev_path(child),base, end);
 228                                         switch(base) {
 229                                         case 0x3f8: // COM1
 230                                                 reg |= (1<<0);  break;
 231                                         case 0x2f8: // COM2
 232                                                 reg |= (1<<1);  break;
 233                                         case 0x378: // Parallal 1
 234                                                 reg |= (1<<24); break;
 235                                         case 0x3f0: // FD0
 236                                                 reg |= (1<<20); break;
 237                                         case 0x220:  // Aduio 0
 238                                                 reg |= (1<<8);  break;
 239                                         case 0x300:  // Midi 0
 240                                                 reg |= (1<<12); break;
 241                                         }
 242                                         if( (base == 0x290) || (base >= 0x400)) {
 243                                                 if(var_num>=4) continue; // only 4 var ; compact them ?
 244                                                 reg |= (1<<(28+var_num));
 245                                                 reg_var[var_num++] = (base & 0xffff)|((end & 0xffff)<<16);
 246                                         }
 247                                 }
 248                         }
 249                 }
 250         }
 251         pci_write_config32(dev, 0xa0, reg);
 252         for(i=0;i<var_num;i++) {
 253                 pci_write_config32(dev, 0xa8 + i*4, reg_var[i]);
 254         }
 255
 256
 257 }
 258
 259 static void mcp55_lpc_enable_resources(device_t dev)
 260 {
 261         pci_dev_enable_resources(dev);
 262         mcp55_lpc_enable_childrens_resources(dev);
 263 }
 264
 265 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 266 {
 267         pci_write_config32(dev, 0x40,
 268                 ((device & 0xffff) << 16) | (vendor & 0xffff));
 269 }
 270
 271 static struct pci_operations lops_pci = {
 272         .set_subsystem  = lpci_set_subsystem,
 273 };
 274
 275 static struct device_operations lpc_ops  = {
 276         .read_resources = mcp55_lpc_read_resources,
 277         .set_resources  = pci_dev_set_resources,
 278         .enable_resources       = mcp55_lpc_enable_resources,
 279         .init           = lpc_init,
 280         .scan_bus       = scan_static_bus,
 281 //      .enable         = mcp55_enable,
 282         .ops_pci        = &lops_pci,
 283 };
 284 static const struct pci_driver lpc_driver __pci_driver = {
 285         .ops    = &lpc_ops,
 286         .vendor = PCI_VENDOR_ID_NVIDIA,
 287         .device = PCI_DEVICE_ID_NVIDIA_MCP55_LPC,
 288 };
 289
 290 static const struct pci_driver lpc_driver_pro __pci_driver = {
 291         .ops    = &lpc_ops,
 292         .vendor = PCI_VENDOR_ID_NVIDIA,
 293         .device = PCI_DEVICE_ID_NVIDIA_MCP55_PRO,
 294 };
 295
 296 static const struct pci_driver lpc_driver_lpc2 __pci_driver = {
 297         .ops    = &lpc_ops,
 298         .vendor = PCI_VENDOR_ID_NVIDIA,
 299         .device = PCI_DEVICE_ID_NVIDIA_MCP55_LPC_2,
 300 };
 301 static const struct pci_driver lpc_driver_lpc3 __pci_driver = {
 302         .ops    = &lpc_ops,
 303         .vendor = PCI_VENDOR_ID_NVIDIA,
 304         .device = PCI_DEVICE_ID_NVIDIA_MCP55_LPC_3,
 305 };
 306 static const struct pci_driver lpc_driver_lpc4 __pci_driver = {
 307         .ops    = &lpc_ops,
 308         .vendor = PCI_VENDOR_ID_NVIDIA,
 309         .device = PCI_DEVICE_ID_NVIDIA_MCP55_LPC_4,
 310 };
 311 static const struct pci_driver lpc_driver_lpc5 __pci_driver = {
 312         .ops    = &lpc_ops,
 313         .vendor = PCI_VENDOR_ID_NVIDIA,
 314         .device = PCI_DEVICE_ID_NVIDIA_MCP55_LPC_5,
 315 };
 316 static const struct pci_driver lpc_driver_lpc6 __pci_driver = {
 317         .ops    = &lpc_ops,
 318         .vendor = PCI_VENDOR_ID_NVIDIA,
 319         .device = PCI_DEVICE_ID_NVIDIA_MCP55_LPC_6,
 320 };
 321
 322 static struct device_operations lpc_slave_ops  = {
 323         .read_resources = mcp55_lpc_read_resources,
 324         .set_resources  = pci_dev_set_resources,
 325         .enable_resources       = pci_dev_enable_resources,
 326         .init           = lpc_slave_init,
 327 //      .enable         = mcp55_enable,
 328         .ops_pci        = &lops_pci,
 329 };
 330
 331 static const struct pci_driver lpc_driver_slave __pci_driver = {
 332         .ops    = &lpc_slave_ops,
 333         .vendor = PCI_VENDOR_ID_NVIDIA,
 334         .device = PCI_DEVICE_ID_NVIDIA_MCP55_SLAVE,
 335 };