2 * This file is part of the coreboot project.
4 * Copyright (C) 2004 Tyan Computer
5 * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
6 * Copyright (C) 2006,2007 AMD
7 * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 #include <console/console.h>
28 #include <device/device.h>
29 #include <device/pci.h>
30 #include <device/pci_ids.h>
31 #include <device/pci_ops.h>
34 static uint32_t final_reg;
36 static device_t find_lpc_dev( device_t dev, unsigned devfn)
41 lpc_dev = dev_find_slot(dev->bus->secondary, devfn);
43 if ( !lpc_dev ) return lpc_dev;
45 if ((lpc_dev->vendor != PCI_VENDOR_ID_NVIDIA) || (
46 (lpc_dev->device < PCI_DEVICE_ID_NVIDIA_MCP55_LPC) ||
47 (lpc_dev->device > PCI_DEVICE_ID_NVIDIA_MCP55_PRO)
50 id = pci_read_config32(lpc_dev, PCI_VENDOR_ID);
51 if ( (id < (PCI_VENDOR_ID_NVIDIA | (PCI_DEVICE_ID_NVIDIA_MCP55_LPC << 16))) ||
52 (id > (PCI_VENDOR_ID_NVIDIA | (PCI_DEVICE_ID_NVIDIA_MCP55_PRO << 16)))
61 void mcp55_enable(device_t dev)
67 uint32_t reg_old, reg;
72 struct southbridge_nvidia_mcp55_config *conf;
73 conf = dev->chip_info;
78 if(dev->device==0x0000) {
79 vendorid = pci_read_config32(dev, PCI_VENDOR_ID);
80 deviceid = (vendorid>>16) & 0xffff;
81 // vendorid &= 0xffff;
83 // vendorid = dev->vendor;
84 deviceid = dev->device;
87 devfn = (dev->path.u.pci.devfn) & ~7;
89 case PCI_DEVICE_ID_NVIDIA_MCP55_HT:
92 case PCI_DEVICE_ID_NVIDIA_MCP55_SM2://?
95 case PCI_DEVICE_ID_NVIDIA_MCP55_USB:
99 case PCI_DEVICE_ID_NVIDIA_MCP55_USB2:
103 case PCI_DEVICE_ID_NVIDIA_MCP55_NIC: //two
104 case PCI_DEVICE_ID_NVIDIA_MCP55_NIC_BRIDGE://two
108 lpc_dev = find_lpc_dev(dev, devfn - (i<<3));
109 if(!lpc_dev) continue;
115 case PCI_DEVICE_ID_NVIDIA_MCP55_AZA:
119 case PCI_DEVICE_ID_NVIDIA_MCP55_IDE:
123 case PCI_DEVICE_ID_NVIDIA_MCP55_SATA0: //three
124 case PCI_DEVICE_ID_NVIDIA_MCP55_SATA1: //three
127 i = (dev->path.u.pci.devfn) & 7;
132 case PCI_DEVICE_ID_NVIDIA_MCP55_PCI:
136 case PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_A:
137 devfn -= (0x9<<3); // to LPC
140 case PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_B_C: //two
141 devfn -= (0xa<<3); // to LPC
144 lpc_dev = find_lpc_dev(dev, devfn - (i<<3));
145 if(!lpc_dev) continue;
151 case PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_D:
152 devfn -= (0xc<<3); // to LPC
155 case PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_E:
156 devfn -= (0xd<<3); // to LPC
159 case PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_F:
160 devfn -= (0xe<<3); // to LPC
168 lpc_dev = find_lpc_dev(dev, devfn);
170 if ( !lpc_dev ) return;
173 sm_dev = dev_find_slot(dev->bus->secondary, devfn + 1);
177 reg_old = reg = pci_read_config32(sm_dev, 0xe4);
179 if (!dev->enabled) { //disable it
183 if (reg != reg_old) {
184 pci_write_config32(sm_dev, 0xe4, reg);
193 if ( index == 0) { // for LPC
195 // expose ioapic base
196 byte = pci_read_config8(lpc_dev, 0x74);
197 byte |= ((1<<1)); // expose the BAR
198 pci_write_config8(dev, 0x74, byte);
201 byte = pci_read_config8(lpc_dev, 0xdd);
202 byte |= ((1<<0)|(1<<3)); // expose the BAR and enable write
203 pci_write_config8(dev, 0xdd, byte);
210 sm_dev = dev_find_slot(dev->bus->secondary, devfn + 1);
213 final_reg = pci_read_config32(sm_dev, 0xe8);
214 final_reg &= ~((1<<16)|(1<<8)|(1<<20)|(1<<14)|(1<<22)|(1<<18)|(1<<17)|(1<<15)|(1<<11)|(1<<10)|(1<<9));
215 pci_write_config32(sm_dev, 0xe8, final_reg); //enable all at first
217 reg_old = reg = pci_read_config32(sm_dev, 0xe4);
220 if (reg != reg_old) {
221 printk_debug("mcp55.c pcie enabled\n");
222 pci_write_config32(sm_dev, 0xe4, reg);
228 final_reg |= (1 << index);// disable it
229 //The reason for using final_reg, if diable func 1, the func 2 will be func 1 so We need disable them one time.
232 if(index == 9 ) { //NIC1 is the final, We need update final reg to 0xe8
233 sm_dev = dev_find_slot(dev->bus->secondary, devfn + 1);
235 reg_old = pci_read_config32(sm_dev, 0xe8);
236 if (final_reg != reg_old) {
237 pci_write_config32(sm_dev, 0xe8, final_reg);
245 struct chip_operations southbridge_nvidia_mcp55_ops = {
246 CHIP_NAME("NVIDIA MCP55 Southbridge")
247 .enable_dev = mcp55_enable,