2 * This file is part of the coreboot project.
4 * Copyright (C) 2008 Advanced Micro Devices, Inc.
5 * Copyright (C) 2008-2010 coresystems GmbH
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <console/console.h>
22 #include <device/device.h>
23 #include <device/pci.h>
24 #include <device/pci_ids.h>
25 #include <device/pci_ops.h>
30 #define HDA_ICII_REG 0x68
31 #define HDA_ICII_BUSY (1 << 0)
32 #define HDA_ICII_VALID (1 << 1)
34 static int set_bits(u32 port, u32 mask, u32 val)
39 /* Write (val & mask) to port */
46 /* Wait for readback of register to
47 * match what was just written to it
51 /* Wait 1ms based on BKDG wait time */
55 } while ((reg32 != val) && --count);
57 /* Timeout occurred */
63 static int codec_detect(u32 base)
67 /* Set Bit0 to 0 to enter reset state (BAR + 0x8)[0] */
68 if (set_bits(base + 0x08, 1, 0) == -1)
71 /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
72 if (set_bits(base + 0x08, 1, 1) == -1)
75 /* Read in Codec location (BAR + 0xe)[2..0]*/
76 reg32 = read32(base + 0xe);
85 /* Put HDA back in reset (BAR + 0x8) [0] */
86 set_bits(base + 0x08, 1, 0);
87 printk(BIOS_DEBUG, "Azalia: No codec!\n");
91 u32 * cim_verb_data = NULL;
92 u32 cim_verb_data_size = 0;
94 static u32 find_verb(struct device *dev, u32 viddid, u32 ** verb)
98 while (idx < (cim_verb_data_size / sizeof(u32))) {
99 u32 verb_size = 4 * cim_verb_data[idx+2]; // in u32
100 if (cim_verb_data[idx] != viddid) {
101 idx += verb_size + 3; // skip verb + header
104 *verb = &cim_verb_data[idx+3];
108 /* Not all codecs need to load another verb */
113 * Wait 50usec for the codec to indicate it is ready
114 * no response would imply that the codec is non-operative
117 static int wait_for_ready(u32 base)
119 /* Use a 50 usec timeout - the Linux kernel uses the
125 u32 reg32 = read32(base + HDA_ICII_REG);
126 if (!(reg32 & HDA_ICII_BUSY))
135 * Wait 50usec for the codec to indicate that it accepted
136 * the previous command. No response would imply that the code
140 static int wait_for_valid(u32 base)
144 /* Send the verb to the codec */
145 reg32 = read32(base + 0x68);
146 reg32 |= (1 << 0) | (1 << 1);
147 write32(base + 0x68, reg32);
149 /* Use a 50 usec timeout - the Linux kernel uses the
154 reg32 = read32(base + HDA_ICII_REG);
155 if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
164 static void codec_init(struct device *dev, u32 base, int addr)
171 printk(BIOS_DEBUG, "Azalia: Initializing codec #%d\n", addr);
174 if (wait_for_ready(base) == -1)
177 reg32 = (addr << 28) | 0x000f0000;
178 write32(base + 0x60, reg32);
180 if (wait_for_valid(base) == -1)
183 reg32 = read32(base + 0x64);
186 printk(BIOS_DEBUG, "Azalia: codec viddid: %08x\n", reg32);
187 verb_size = find_verb(dev, reg32, &verb);
190 printk(BIOS_DEBUG, "Azalia: No verb!\n");
193 printk(BIOS_DEBUG, "Azalia: verb_size: %d\n", verb_size);
196 for (i = 0; i < verb_size; i++) {
197 if (wait_for_ready(base) == -1)
200 write32(base + 0x60, verb[i]);
202 if (wait_for_valid(base) == -1)
205 printk(BIOS_DEBUG, "Azalia: verb loaded.\n");
208 static void codecs_init(struct device *dev, u32 base, u32 codec_mask)
211 for (i = 2; i >= 0; i--) {
212 if (codec_mask & (1 << i))
213 codec_init(dev, base, i);
217 static void azalia_init(struct device *dev)
220 struct resource *res;
226 reg32 = pci_read_config32(dev, PCI_COMMAND);
227 pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);
229 pci_write_config8(dev, 0x3c, 0x0a); // unused?
231 reg8 = pci_read_config8(dev, 0x40);
232 reg8 |= (1 << 3); // Clear Clock Detect Bit
233 pci_write_config8(dev, 0x40, reg8);
234 reg8 &= ~(1 << 3); // Keep CLKDETCLR from clearing the bit over and over
235 pci_write_config8(dev, 0x40, reg8);
236 reg8 |= (1 << 2); // Enable clock detection
237 pci_write_config8(dev, 0x40, reg8);
239 reg8 = pci_read_config8(dev, 0x40);
240 printk(BIOS_DEBUG, "Azalia: codec type: %s\n", (reg8 & (1 << 1))?"Azalia":"AC97");
243 reg8 = pci_read_config8(dev, 0x40); // Audio Control
244 reg8 |= 1; // Select Azalia mode. This needs to be controlled via devicetree.cb
245 pci_write_config8(dev, 0x40, reg8);
247 reg8 = pci_read_config8(dev, 0x4d); // Docking Status
248 reg8 &= ~(1 << 7); // Docking not supported
249 pci_write_config8(dev, 0x4d, reg8);
251 res = find_resource(dev, 0x10);
255 // NOTE this will break as soon as the Azalia get's a bar above
256 // 4G. Is there anything we can do about it?
257 base = (u32)res->base;
258 printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base);
259 codec_mask = codec_detect(base);
262 printk(BIOS_DEBUG, "Azalia: codec_mask = %02x\n", codec_mask);
263 codecs_init(dev, base, codec_mask);
267 static void azalia_set_subsystem(device_t dev, unsigned vendor, unsigned device)
269 if (!vendor || !device) {
270 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
271 pci_read_config32(dev, PCI_VENDOR_ID));
273 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
274 ((device & 0xffff) << 16) | (vendor & 0xffff));
278 static struct pci_operations azalia_pci_ops = {
279 .set_subsystem = azalia_set_subsystem,
282 static struct device_operations azalia_ops = {
283 .read_resources = pci_dev_read_resources,
284 .set_resources = pci_dev_set_resources,
285 .enable_resources = pci_dev_enable_resources,
288 // .enable = mcp55_enable,
289 .ops_pci = &azalia_pci_ops,
292 static const struct pci_driver azalia __pci_driver = {
294 .vendor = PCI_VENDOR_ID_NVIDIA,
295 .device = PCI_DEVICE_ID_NVIDIA_MCP55_AZA,