src/southbridge/nvidia/ck804/nic.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2004 Tyan Computer
   5  * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  19  */
  20
  21 #include <console/console.h>
  22 #include <device/device.h>
  23 #include <device/smbus.h>
  24 #include <device/pci.h>
  25 #include <device/pci_ids.h>
  26 #include <device/pci_ops.h>
  27 #include <arch/io.h>
  28 #include "ck804.h"
  29
  30 static void nic_init(struct device *dev)
  31 {
  32         u32 dword, old, mac_h, mac_l;
  33         int eeprom_valid = 0;
  34         struct southbridge_nvidia_ck804_config *conf;
  35         static u32 nic_index = 0;
  36         unsigned long base;
  37         struct resource *res;
  38
  39         res = find_resource(dev, 0x10);
  40         base = (unsigned long)res->base;
  41
  42 #define NvRegPhyInterface  0xC0
  43 #define PHY_RGMII          0x10000000
  44
  45         write32(base + NvRegPhyInterface, PHY_RGMII);
  46
  47         old = dword = pci_read_config32(dev, 0x30);
  48         dword &= ~(0xf);
  49         dword |= 0xf;
  50         if (old != dword)
  51                 pci_write_config32(dev, 0x30, dword);
  52
  53         conf = dev->chip_info;
  54
  55         if (conf->mac_eeprom_smbus != 0) {
  56                 /* Read MAC address from EEPROM at first. */
  57                 struct device *dev_eeprom;
  58                 dev_eeprom = dev_find_slot_on_smbus(conf->mac_eeprom_smbus,
  59                                            conf->mac_eeprom_addr);
  60
  61                 if (dev_eeprom) {
  62                         /* If that is valid we will use that. */
  63                         unsigned char dat[6];
  64                         int i, status;
  65                         for (i = 0; i < 6; i++) {
  66                                 status = smbus_read_byte(dev_eeprom, i);
  67                                 if (status < 0)
  68                                         break;
  69                                 dat[i] = status & 0xff;
  70                         }
  71                         if (status >= 0) {
  72                                 mac_l = 0;
  73                                 for (i = 3; i >= 0; i--) {
  74                                         mac_l <<= 8;
  75                                         mac_l += dat[i];
  76                                 }
  77                                 if (mac_l != 0xffffffff) {
  78                                         mac_l += nic_index;
  79                                         mac_h = 0;
  80                                         for (i = 5; i >= 4; i--) {
  81                                                 mac_h <<= 8;
  82                                                 mac_h += dat[i];
  83                                         }
  84                                         eeprom_valid = 1;
  85                                 }
  86                         }
  87                 }
  88         }
  89
  90         /* If that is invalid we will read that from romstrap. */
  91         if (!eeprom_valid) {
  92                 unsigned long mac_pos;
  93                 mac_pos = 0xffffffd0; /* See romstrap.inc and romstrap.lds. */
  94                 mac_l = read32(mac_pos) + nic_index;
  95                 mac_h = read32(mac_pos + 4);
  96         }
  97 #if 1
  98         /* Set that into NIC MMIO. */
  99 #define NvRegMacAddrA  0xA8
 100 #define NvRegMacAddrB  0xAC
 101         write32(base + NvRegMacAddrA, mac_l);
 102         write32(base + NvRegMacAddrB, mac_h);
 103 #else
 104         /* Set that into NIC. */
 105         pci_write_config32(dev, 0xa8, mac_l);
 106         pci_write_config32(dev, 0xac, mac_h);
 107 #endif
 108
 109         nic_index++;
 110
 111 #if CONFIG_PCI_ROM_RUN == 1
 112         pci_dev_init(dev);      /* It will init Option ROM. */
 113 #endif
 114 }
 115
 116 static struct device_operations nic_ops = {
 117         .read_resources   = pci_dev_read_resources,
 118         .set_resources    = pci_dev_set_resources,
 119         .enable_resources = pci_dev_enable_resources,
 120         .init             = nic_init,
 121         .scan_bus         = 0,
 122         // .enable        = ck804_enable,
 123         .ops_pci          = &ck804_pci_ops,
 124 };
 125
 126 static const struct pci_driver nic_driver __pci_driver = {
 127         .ops    = &nic_ops,
 128         .vendor = PCI_VENDOR_ID_NVIDIA,
 129         .device = PCI_DEVICE_ID_NVIDIA_CK804_NIC,
 130 };
 131
 132 static const struct pci_driver nic_bridge_driver __pci_driver = {
 133         .ops    = &nic_ops,
 134         .vendor = PCI_VENDOR_ID_NVIDIA,
 135         .device = PCI_DEVICE_ID_NVIDIA_CK804_NIC_BRIDGE,
 136 };