src/southbridge/nvidia/ck804/lpc.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2003 Linux Networx
   5  * Copyright (C) 2003 SuSE Linux AG
   6  * Copyright (C) 2004 Tyan Computer
   7  * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; version 2 of the License.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  21  */
  22
  23 #include <console/console.h>
  24 #include <device/device.h>
  25 #include <device/pci.h>
  26 #include <device/pnp.h>
  27 #include <device/pci_ids.h>
  28 #include <device/pci_ops.h>
  29 #include <pc80/mc146818rtc.h>
  30 #include <pc80/isa-dma.h>
  31 #include <bitops.h>
  32 #include <arch/io.h>
  33 #include <arch/ioapic.h>
  34 #include <cpu/x86/lapic.h>
  35 #include <stdlib.h>
  36 #include "ck804.h"
  37
  38 #define CK804_CHIP_REV 2
  39
  40 #define NMI_OFF 0
  41
  42 // 0x7a or e3
  43 #define PREVIOUS_POWER_STATE 0x7A
  44
  45 #define MAINBOARD_POWER_OFF 0
  46 #define MAINBOARD_POWER_ON 1
  47 #define SLOW_CPU_OFF 0
  48 #define SLOW_CPU__ON 1
  49
  50 #ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
  51 #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
  52 #endif
  53
  54 static void lpc_common_init(device_t dev)
  55 {
  56         u8 byte;
  57         u32 dword;
  58
  59         /* I/O APIC initialization. */
  60         byte = pci_read_config8(dev, 0x74);
  61         byte |= (1 << 0);       /* Enable APIC. */
  62         pci_write_config8(dev, 0x74, byte);
  63         dword = pci_read_config32(dev, PCI_BASE_ADDRESS_1);     /* 0x14 */
  64
  65         setup_ioapic(dword, 0); /* Don't rename IOAPIC ID. */
  66
  67 #if 1
  68         dword = pci_read_config32(dev, 0xe4);
  69         dword |= (1 << 23);
  70         pci_write_config32(dev, 0xe4, dword);
  71 #endif
  72 }
  73
  74 static void lpc_slave_init(device_t dev)
  75 {
  76         lpc_common_init(dev);
  77 }
  78
  79 static void rom_dummy_write(device_t dev)
  80 {
  81         u8 old, new;
  82         u8 *p;
  83
  84         old = pci_read_config8(dev, 0x88);
  85         new = old | 0xc0;
  86         if (new != old)
  87                 pci_write_config8(dev, 0x88, new);
  88         /* Enable write. */
  89         old = pci_read_config8(dev, 0x6d);
  90         new = old | 0x01;
  91         if (new != old)
  92                 pci_write_config8(dev, 0x6d, new);
  93
  94         /* Dummy write. */
  95         p = (u8 *) 0xffffffe0;
  96         old = 0;
  97         *p = old;
  98         old = *p;
  99
 100         /* Disable write. */
 101         old = pci_read_config8(dev, 0x6d);
 102         new = old & 0xfe;
 103         if (new != old)
 104                 pci_write_config8(dev, 0x6d, new);
 105 }
 106
 107 unsigned pm_base = 0;
 108
 109 static void lpc_init(device_t dev)
 110 {
 111         u8 byte, byte_old;
 112         int on, nmi_option;
 113
 114         lpc_common_init(dev);
 115
 116         pm_base = pci_read_config32(dev, 0x60) & 0xff00;
 117         printk(BIOS_INFO, "%s: pm_base = %x \n", __func__, pm_base);
 118
 119 #if CK804_CHIP_REV == 1
 120         if (dev->bus->secondary != 1)
 121                 return;
 122 #endif
 123
 124         /* Power after power fail */
 125         on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
 126         get_option(&on, "power_on_after_fail");
 127         byte = pci_read_config8(dev, PREVIOUS_POWER_STATE);
 128         byte &= ~0x40;
 129         if (!on)
 130                 byte |= 0x40;
 131         pci_write_config8(dev, PREVIOUS_POWER_STATE, byte);
 132         printk(BIOS_INFO, "set power %s after power fail\n", on ? "on" : "off");
 133
 134         /* Throttle the CPU speed down for testing. */
 135         on = SLOW_CPU_OFF;
 136         get_option(&on, "slow_cpu");
 137         if (on) {
 138                 u16 pm10_bar;
 139                 u32 dword;
 140                 pm10_bar = (pci_read_config16(dev, 0x60) & 0xff00);
 141                 outl(((on << 1) + 0x10), (pm10_bar + 0x10));
 142                 dword = inl(pm10_bar + 0x10);
 143                 on = 8 - on;
 144                 printk(BIOS_DEBUG, "Throttling CPU %2d.%1.1d percent.\n",
 145                        (on * 12) + (on >> 1), (on & 1) * 5);
 146         }
 147 #if 0
 148         /* Enable Port 92 fast reset (default is enabled). */
 149         byte = pci_read_config8(dev, 0xe8);
 150         byte |= ~(1 << 3);
 151         pci_write_config8(dev, 0xe8, byte);
 152 #endif
 153
 154         /* Set up NMI on errors. */
 155         byte = inb(0x70);               /* RTC70 */
 156         byte_old = byte;
 157         nmi_option = NMI_OFF;
 158         get_option(&nmi_option, "nmi");
 159         if (nmi_option)
 160                 byte &= ~(1 << 7); /* Set NMI. */
 161         else
 162                 byte |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW. */
 163         if (byte != byte_old)
 164                 outb(byte, 0x70);
 165
 166         /* Initialize the real time clock (RTC). */
 167         rtc_init(0);
 168
 169         /* Initialize ISA DMA. */
 170         isa_dma_init();
 171
 172         rom_dummy_write(dev);
 173 }
 174
 175 static void ck804_lpc_read_resources(device_t dev)
 176 {
 177         struct resource *res;
 178         unsigned long index;
 179
 180         /* Get the normal PCI resources of this device. */
 181         /* We got one for APIC, or one more for TRAP. */
 182         pci_dev_read_resources(dev);
 183
 184         /* HPET */
 185         pci_get_resource(dev, 0x44);
 186
 187         /* Get resource for ACPI, SYSTEM_CONTROL, ANALOG_CONTROL. */
 188         for (index = 0x60; index <= 0x68; index += 4)   /* We got another 3. */
 189                 pci_get_resource(dev, index);
 190         compact_resources(dev);
 191
 192         /* Add an extra subtractive resource for both memory and I/O. */
 193         res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
 194         res->base = 0;
 195         res->size = 0x1000;
 196         res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
 197                      IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 198
 199         res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
 200         res->base = 0xff800000;
 201         res->size = 0x00800000; /* 8 MB for flash */
 202         res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
 203                      IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 204
 205         if (dev->device != PCI_DEVICE_ID_NVIDIA_CK804_SLAVE) {
 206                 res = find_resource(dev, 0x14); /* IOAPIC */
 207                 if (res) {
 208                         res->base = IO_APIC_ADDR;
 209                         res->flags |= IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 210                 }
 211
 212                 res = find_resource(dev, 0x44); /* HPET */
 213                 if (res) {
 214                         res->base = 0xfed00000;
 215                         res->flags |= IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 216                 }
 217         }
 218 }
 219
 220 static void ck804_lpc_set_resources(device_t dev)
 221 {
 222         struct resource *res;
 223
 224         pci_dev_set_resources(dev);
 225
 226         /* APIC */
 227         res = find_resource(dev, 0x14);
 228         if (res) {
 229                 pci_write_config32(dev, 0x14, res->base);
 230                 res->flags |= IORESOURCE_STORED;
 231                 report_resource_stored(dev, res, "");
 232         }
 233
 234         /* HPET */
 235         res = find_resource(dev, 0x44);
 236         if (res) {
 237                 pci_write_config32(dev, 0x44, res->base|1);
 238                 res->flags |= IORESOURCE_STORED;
 239                 report_resource_stored(dev, res, "");
 240         }
 241 }
 242
 243 /**
 244  * Enable resources for children devices.
 245  *
 246  * This function is called by the global enable_resources() indirectly via the
 247  * device_operation::enable_resources() method of devices.
 248  */
 249 static void ck804_lpc_enable_childrens_resources(device_t dev)
 250 {
 251         struct bus *link;
 252         u32 reg, reg_var[4];
 253         int i, var_num = 0;
 254
 255         reg = pci_read_config32(dev, 0xa0);
 256
 257         for (link = dev->link_list; link; link = link->next) {
 258                 device_t child;
 259                 for (child = link->children; child; child = child->sibling) {
 260                         if (child->enabled && (child->path.type == DEVICE_PATH_PNP)) {
 261                                 struct resource *res;
 262                                 for (res = child->resource_list; res; res = res->next) {
 263                                         unsigned long base, end; /* Don't need long long. */
 264                                         if (!(res->flags & IORESOURCE_IO))
 265                                                 continue;
 266                                         base = res->base;
 267                                         end = resource_end(res);
 268                                         printk(BIOS_DEBUG, "ck804 lpc decode:%s, base=0x%08lx, end=0x%08lx\n", dev_path(child), base, end);
 269                                         switch (base) {
 270                                         case 0x3f8:     // COM1
 271                                                 reg |= (1 << 0);
 272                                                 break;
 273                                         case 0x2f8:     // COM2
 274                                                 reg |= (1 << 1);
 275                                                 break;
 276                                         case 0x378:     // Parallel 1
 277                                                 reg |= (1 << 24);
 278                                                 break;
 279                                         case 0x3f0:     // FD0
 280                                                 reg |= (1 << 20);
 281                                                 break;
 282                                         case 0x220:     // Audio 0
 283                                                 reg |= (1 << 8);
 284                                                 break;
 285                                         case 0x300:     // Midi 0
 286                                                 reg |= (1 << 12);
 287                                                 break;
 288                                         }
 289                                         if (base == 0x290 || base >= 0x400) {
 290                                                 /* Only 4 var; compact them? */
 291                                                 if (var_num >= 4)
 292                                                         continue;
 293                                                 reg |= (1 << (28 + var_num));
 294                                                 reg_var[var_num++] = (base & 0xffff) | ((end & 0xffff) << 16);
 295                                         }
 296                                 }
 297                         }
 298                 }
 299         }
 300         pci_write_config32(dev, 0xa0, reg);
 301         for (i = 0; i < var_num; i++)
 302                 pci_write_config32(dev, 0xa8 + i * 4, reg_var[i]);
 303 }
 304
 305 static void ck804_lpc_enable_resources(device_t dev)
 306 {
 307         pci_dev_enable_resources(dev);
 308         ck804_lpc_enable_childrens_resources(dev);
 309 }
 310
 311 static struct device_operations lpc_ops = {
 312         .read_resources   = ck804_lpc_read_resources,
 313         .set_resources    = ck804_lpc_set_resources,
 314         .enable_resources = ck804_lpc_enable_resources,
 315         .init             = lpc_init,
 316         .scan_bus         = scan_static_bus,
 317         // .enable        = ck804_enable,
 318         .ops_pci          = &ck804_pci_ops,
 319 };
 320
 321 static const struct pci_driver lpc_driver __pci_driver = {
 322         .ops    = &lpc_ops,
 323         .vendor = PCI_VENDOR_ID_NVIDIA,
 324         .device = PCI_DEVICE_ID_NVIDIA_CK804_LPC,
 325 };
 326
 327 static const struct pci_driver lpc_driver_pro __pci_driver = {
 328         .ops    = &lpc_ops,
 329         .vendor = PCI_VENDOR_ID_NVIDIA,
 330         .device = PCI_DEVICE_ID_NVIDIA_CK804_PRO,
 331 };
 332
 333 #if CK804_CHIP_REV == 1
 334 static const struct pci_driver lpc_driver_slave __pci_driver = {
 335         .ops    = &lpc_ops,
 336         .vendor = PCI_VENDOR_ID_NVIDIA,
 337         .device = PCI_DEVICE_ID_NVIDIA_CK804_SLAVE,
 338 };
 339 #else
 340 static struct device_operations lpc_slave_ops = {
 341         .read_resources   = ck804_lpc_read_resources,
 342         .set_resources    = pci_dev_set_resources,
 343         .enable_resources = pci_dev_enable_resources,
 344         .init             = lpc_slave_init,
 345         // .enable        = ck804_enable,
 346         .ops_pci          = &ck804_pci_ops,
 347 };
 348
 349 static const struct pci_driver lpc_driver_slave __pci_driver = {
 350         .ops    = &lpc_slave_ops,
 351         .vendor = PCI_VENDOR_ID_NVIDIA,
 352         .device = PCI_DEVICE_ID_NVIDIA_CK804_SLAVE,
 353 };
 354 #endif