src/southbridge/nvidia/ck804/lpc.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2003 Linux Networx
   5  * Copyright (C) 2003 SuSE Linux AG
   6  * Copyright (C) 2004 Tyan Computer
   7  * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; version 2 of the License.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  21  */
  22
  23 #include <console/console.h>
  24 #include <device/device.h>
  25 #include <device/pci.h>
  26 #include <device/pnp.h>
  27 #include <device/pci_ids.h>
  28 #include <device/pci_ops.h>
  29 #include <pc80/mc146818rtc.h>
  30 #include <pc80/isa-dma.h>
  31 #include <bitops.h>
  32 #include <arch/io.h>
  33 #include <arch/ioapic.h>
  34 #include <cpu/x86/lapic.h>
  35 #include <stdlib.h>
  36 #include "ck804.h"
  37
  38 #define CK804_CHIP_REV 2
  39
  40 #define NMI_OFF 0
  41
  42 // 0x7a or e3
  43 #define PREVIOUS_POWER_STATE 0x7A
  44
  45 #define MAINBOARD_POWER_OFF 0
  46 #define MAINBOARD_POWER_ON 1
  47 #define SLOW_CPU_OFF 0
  48 #define SLOW_CPU__ON 1
  49
  50 #ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
  51 #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
  52 #endif
  53
  54 static void lpc_common_init(device_t dev)
  55 {
  56         uint8_t byte;
  57         uint32_t dword;
  58
  59         /* I/O APIC initialization */
  60         byte = pci_read_config8(dev, 0x74);
  61         byte |= (1 << 0);       /* Enable APIC. */
  62         pci_write_config8(dev, 0x74, byte);
  63         dword = pci_read_config32(dev, PCI_BASE_ADDRESS_1);     /* 0x14 */
  64
  65         setup_ioapic(dword, 0); // Don't rename IOAPIC ID
  66
  67 #if 1
  68         dword = pci_read_config32(dev, 0xe4);
  69         dword |= (1 << 23);
  70         pci_write_config32(dev, 0xe4, dword);
  71 #endif
  72 }
  73
  74 static void lpc_slave_init(device_t dev)
  75 {
  76         lpc_common_init(dev);
  77 }
  78
  79 static void rom_dummy_write(device_t dev)
  80 {
  81         uint8_t old, new;
  82         uint8_t *p;
  83
  84         old = pci_read_config8(dev, 0x88);
  85         new = old | 0xc0;
  86         if (new != old)
  87                 pci_write_config8(dev, 0x88, new);
  88         /* Enable write. */
  89         old = pci_read_config8(dev, 0x6d);
  90         new = old | 0x01;
  91         if (new != old)
  92                 pci_write_config8(dev, 0x6d, new);
  93
  94         /* Dummy write. */
  95         p = (uint8_t *) 0xffffffe0;
  96         old = 0;
  97         *p = old;
  98         old = *p;
  99
 100         /* Disable write. */
 101         old = pci_read_config8(dev, 0x6d);
 102         new = old & 0xfe;
 103         if (new != old)
 104                 pci_write_config8(dev, 0x6d, new);
 105 }
 106
 107 static void enable_hpet(struct device *dev)
 108 {
 109         unsigned long hpet_address;
 110
 111         pci_write_config32(dev, 0x44, 0xfed00001);
 112         hpet_address = pci_read_config32(dev, 0x44) & 0xfffffffe;
 113         printk(BIOS_DEBUG, "Enabling HPET @0x%lx\n", hpet_address);
 114 }
 115
 116 unsigned pm_base=0;
 117
 118 static void lpc_init(device_t dev)
 119 {
 120         uint8_t byte, byte_old;
 121         int on, nmi_option;
 122
 123         lpc_common_init(dev);
 124
 125         pm_base = pci_read_config32(dev, 0x60) & 0xff00;
 126         printk(BIOS_INFO, "%s: pm_base = %x \n", __func__, pm_base);
 127
 128 #if CK804_CHIP_REV==1
 129         if (dev->bus->secondary != 1)
 130                 return;
 131 #endif
 132
 133 #if 0
 134         /* Posted memory write enable */
 135         byte = pci_read_config8(dev, 0x46);
 136         pci_write_config8(dev, 0x46, byte | (1 << 0));
 137 #endif
 138
 139         /* power after power fail */
 140         on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
 141         get_option(&on, "power_on_after_fail");
 142         byte = pci_read_config8(dev, PREVIOUS_POWER_STATE);
 143         byte &= ~0x40;
 144         if (!on)
 145                 byte |= 0x40;
 146         pci_write_config8(dev, PREVIOUS_POWER_STATE, byte);
 147         printk(BIOS_INFO, "set power %s after power fail\n", on ? "on" : "off");
 148
 149         /* Throttle the CPU speed down for testing. */
 150         on = SLOW_CPU_OFF;
 151         get_option(&on, "slow_cpu");
 152         if (on) {
 153                 uint16_t pm10_bar;
 154                 uint32_t dword;
 155                 pm10_bar = (pci_read_config16(dev, 0x60) & 0xff00);
 156                 outl(((on << 1) + 0x10), (pm10_bar + 0x10));
 157                 dword = inl(pm10_bar + 0x10);
 158                 on = 8 - on;
 159                 printk(BIOS_DEBUG, "Throttling CPU %2d.%1.1d percent.\n",
 160                              (on * 12) + (on >> 1), (on & 1) * 5);
 161         }
 162 #if 0
 163 // default is enabled
 164         /* Enable Port 92 fast reset. */
 165         byte = pci_read_config8(dev, 0xe8);
 166         byte |= ~(1 << 3);
 167         pci_write_config8(dev, 0xe8, byte);
 168 #endif
 169
 170         /* Enable Error reporting. */
 171         /* Set up sync flood detected. */
 172         byte = pci_read_config8(dev, 0x47);
 173         byte |= (1 << 1);
 174         pci_write_config8(dev, 0x47, byte);
 175
 176         /* Set up NMI on errors. */
 177         byte = inb(0x70);               /* RTC70 */
 178         byte_old = byte;
 179         nmi_option = NMI_OFF;
 180         get_option(&nmi_option, "nmi");
 181         if (nmi_option) {
 182                 byte &= ~(1 << 7); /* Set NMI. */
 183         } else {
 184                 byte |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW. */
 185         }
 186         if (byte != byte_old)
 187                 outb(byte, 0x70);
 188
 189         /* Initialize the real time clock (RTC). */
 190         rtc_init(0);
 191
 192         /* Initialize ISA DMA. */
 193         isa_dma_init();
 194
 195         /* Initialize the High Precision Event Timers (HPET). */
 196         enable_hpet(dev);
 197
 198         rom_dummy_write(dev);
 199 }
 200
 201 static void ck804_lpc_read_resources(device_t dev)
 202 {
 203         struct resource *res;
 204         unsigned long index;
 205
 206         /* Get the normal PCI resources of this device. */
 207         /* We got one for APIC, or one more for TRAP. */
 208         pci_dev_read_resources(dev);
 209
 210         /* Get resource for ACPI, SYSTEM_CONTROL, ANALOG_CONTROL. */
 211         for (index = 0x60; index <= 0x68; index += 4)   /* We got another 3. */
 212                 pci_get_resource(dev, index);
 213         compact_resources(dev);
 214
 215         /* Add an extra subtractive resource for both memory and I/O. */
 216         res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
 217         res->base = 0;
 218         res->size = 0x1000;
 219         res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
 220                      IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 221
 222         res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
 223         res->base = 0xff800000;
 224         res->size = 0x00800000; /* 8 MB for flash */
 225         res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
 226                      IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 227
 228         res = new_resource(dev, 3); /* IOAPIC */
 229         res->base = IO_APIC_ADDR;
 230         res->size = 0x00001000;
 231         res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 232 }
 233
 234 /**
 235  * Enable resources for children devices.
 236  *
 237  * This function is called by the global enable_resources() indirectly via the
 238  * device_operation::enable_resources() method of devices.
 239  *
 240  */
 241 static void ck804_lpc_enable_childrens_resources(device_t dev)
 242 {
 243         struct bus *link;
 244         uint32_t reg, reg_var[4];
 245         int i, var_num = 0;
 246
 247         reg = pci_read_config32(dev, 0xa0);
 248
 249         for (link = dev->link_list; link; link = link->next) {
 250                 device_t child;
 251                 for (child = link->children; child; child = child->sibling) {
 252                         if (child->enabled && (child->path.type == DEVICE_PATH_PNP)) {
 253                                 struct resource *res;
 254                                 for (res = child->resource_list; res; res = res->next) {
 255                                         unsigned long base, end;        // don't need long long
 256                                         if (!(res->flags & IORESOURCE_IO))
 257                                                 continue;
 258                                         base = res->base;
 259                                         end = resource_end(res);
 260                                         printk(BIOS_DEBUG, "ck804 lpc decode:%s, base=0x%08lx, end=0x%08lx\n", dev_path(child), base, end);
 261                                         switch (base) {
 262                                         case 0x3f8:     // COM1
 263                                                 reg |= (1 << 0);
 264                                                 break;
 265                                         case 0x2f8:     // COM2
 266                                                 reg |= (1 << 1);
 267                                                 break;
 268                                         case 0x378:     // Parallel 1
 269                                                 reg |= (1 << 24);
 270                                                 break;
 271                                         case 0x3f0:     // FD0
 272                                                 reg |= (1 << 20);
 273                                                 break;
 274                                         case 0x220:     // Audio 0
 275                                                 reg |= (1 << 8);
 276                                                 break;
 277                                         case 0x300:     // Midi 0
 278                                                 reg |= (1 << 12);
 279                                                 break;
 280                                         }
 281                                         if (base == 0x290 || base >= 0x400) {
 282                                                 if (var_num >= 4)
 283                                                         continue;       // only 4 var ; compact them ?
 284                                                 reg |= (1 << (28 + var_num));
 285                                                 reg_var[var_num++] = (base & 0xffff) | ((end & 0xffff) << 16);
 286                                         }
 287                                 }
 288                         }
 289                 }
 290         }
 291         pci_write_config32(dev, 0xa0, reg);
 292         for (i = 0; i < var_num; i++)
 293                 pci_write_config32(dev, 0xa8 + i * 4, reg_var[i]);
 294 }
 295
 296 static void ck804_lpc_enable_resources(device_t dev)
 297 {
 298         pci_dev_enable_resources(dev);
 299         ck804_lpc_enable_childrens_resources(dev);
 300 }
 301
 302 static struct device_operations lpc_ops = {
 303         .read_resources   = ck804_lpc_read_resources,
 304         .set_resources    = pci_dev_set_resources,
 305         .enable_resources = ck804_lpc_enable_resources,
 306         .init             = lpc_init,
 307         .scan_bus         = scan_static_bus,
 308         // .enable        = ck804_enable,
 309         .ops_pci          = &ck804_pci_ops,
 310 };
 311
 312 static const struct pci_driver lpc_driver __pci_driver = {
 313         .ops    = &lpc_ops,
 314         .vendor = PCI_VENDOR_ID_NVIDIA,
 315         .device = PCI_DEVICE_ID_NVIDIA_CK804_LPC,
 316 };
 317
 318 static const struct pci_driver lpc_driver_pro __pci_driver = {
 319         .ops    = &lpc_ops,
 320         .vendor = PCI_VENDOR_ID_NVIDIA,
 321         .device = PCI_DEVICE_ID_NVIDIA_CK804_PRO,
 322 };
 323
 324 #if CK804_CHIP_REV == 1
 325 static const struct pci_driver lpc_driver_slave __pci_driver = {
 326         .ops    = &lpc_ops,
 327         .vendor = PCI_VENDOR_ID_NVIDIA,
 328         .device = PCI_DEVICE_ID_NVIDIA_CK804_SLAVE,
 329 };
 330 #else
 331 static struct device_operations lpc_slave_ops = {
 332         .read_resources   = ck804_lpc_read_resources,
 333         .set_resources    = pci_dev_set_resources,
 334         .enable_resources = pci_dev_enable_resources,
 335         .init             = lpc_slave_init,
 336         // .enable        = ck804_enable,
 337         .ops_pci          = &ck804_pci_ops,
 338 };
 339
 340 static const struct pci_driver lpc_driver_slave __pci_driver = {
 341         .ops    = &lpc_slave_ops,
 342         .vendor = PCI_VENDOR_ID_NVIDIA,
 343         .device = PCI_DEVICE_ID_NVIDIA_CK804_SLAVE,
 344 };
 345 #endif