src/southbridge/nvidia/ck804/ck804_lpc.c

   1 /*
   2  * (C) 2003 Linux Networx, SuSE Linux AG
   3  * Copyright 2004 Tyan Computer
   4  *  by yhlu@tyan.com
   5  *  2006.1 yhlu add dest apicid for IRQ0
   6  */
   7
   8 #include <console/console.h>
   9 #include <device/device.h>
  10 #include <device/pci.h>
  11 #include <device/pnp.h>
  12 #include <device/pci_ids.h>
  13 #include <device/pci_ops.h>
  14 #include <pc80/mc146818rtc.h>
  15 #include <pc80/isa-dma.h>
  16 #include <bitops.h>
  17 #include <arch/io.h>
  18 #include <arch/ioapic.h>
  19 #include <cpu/x86/lapic.h>
  20 #include <stdlib.h>
  21 #include "ck804.h"
  22
  23 #define CK804_CHIP_REV 2
  24
  25 #define NMI_OFF 0
  26
  27 // 0x7a or e3
  28 #define PREVIOUS_POWER_STATE 0x7A
  29
  30 #define MAINBOARD_POWER_OFF 0
  31 #define MAINBOARD_POWER_ON 1
  32 #define SLOW_CPU_OFF 0
  33 #define SLOW_CPU__ON 1
  34
  35 #ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
  36 #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
  37 #endif
  38
  39 static void lpc_common_init(device_t dev)
  40 {
  41         uint8_t byte;
  42         uint32_t dword;
  43
  44         /* I/O APIC initialization */
  45         byte = pci_read_config8(dev, 0x74);
  46         byte |= (1 << 0);       /* Enable APIC. */
  47         pci_write_config8(dev, 0x74, byte);
  48         dword = pci_read_config32(dev, PCI_BASE_ADDRESS_1);     /* 0x14 */
  49
  50         setup_ioapic(dword, 0); // Don't rename IOAPIC ID
  51
  52 #if 1
  53         dword = pci_read_config32(dev, 0xe4);
  54         dword |= (1 << 23);
  55         pci_write_config32(dev, 0xe4, dword);
  56 #endif
  57 }
  58
  59 static void lpc_slave_init(device_t dev)
  60 {
  61         lpc_common_init(dev);
  62 }
  63
  64 static void rom_dummy_write(device_t dev)
  65 {
  66         uint8_t old, new;
  67         uint8_t *p;
  68
  69         old = pci_read_config8(dev, 0x88);
  70         new = old | 0xc0;
  71         if (new != old)
  72                 pci_write_config8(dev, 0x88, new);
  73         /* Enable write. */
  74         old = pci_read_config8(dev, 0x6d);
  75         new = old | 0x01;
  76         if (new != old)
  77                 pci_write_config8(dev, 0x6d, new);
  78
  79         /* Dummy write. */
  80         p = (uint8_t *) 0xffffffe0;
  81         old = 0;
  82         *p = old;
  83         old = *p;
  84
  85         /* Disable write. */
  86         old = pci_read_config8(dev, 0x6d);
  87         new = old & 0xfe;
  88         if (new != old)
  89                 pci_write_config8(dev, 0x6d, new);
  90 }
  91
  92 static void enable_hpet(struct device *dev)
  93 {
  94         unsigned long hpet_address;
  95
  96         pci_write_config32(dev, 0x44, 0xfed00001);
  97         hpet_address = pci_read_config32(dev, 0x44) & 0xfffffffe;
  98         printk_debug("Enabling HPET @0x%lx\n", hpet_address);
  99 }
 100
 101 unsigned pm_base=0;
 102
 103 static void lpc_init(device_t dev)
 104 {
 105         uint8_t byte, byte_old;
 106         int on, nmi_option;
 107
 108         lpc_common_init(dev);
 109
 110         pm_base = pci_read_config32(dev, 0x60) & 0xff00;
 111         printk_info("%s: pm_base = %x \n", __func__, pm_base);
 112
 113 #if CK804_CHIP_REV==1
 114         if (dev->bus->secondary != 1)
 115                 return;
 116 #endif
 117
 118 #if 0
 119         /* Posted memory write enable */
 120         byte = pci_read_config8(dev, 0x46);
 121         pci_write_config8(dev, 0x46, byte | (1 << 0));
 122 #endif
 123
 124         /* power after power fail */
 125         on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
 126         get_option(&on, "power_on_after_fail");
 127         byte = pci_read_config8(dev, PREVIOUS_POWER_STATE);
 128         byte &= ~0x40;
 129         if (!on)
 130                 byte |= 0x40;
 131         pci_write_config8(dev, PREVIOUS_POWER_STATE, byte);
 132         printk_info("set power %s after power fail\n", on ? "on" : "off");
 133
 134         /* Throttle the CPU speed down for testing. */
 135         on = SLOW_CPU_OFF;
 136         get_option(&on, "slow_cpu");
 137         if (on) {
 138                 uint16_t pm10_bar;
 139                 uint32_t dword;
 140                 pm10_bar = (pci_read_config16(dev, 0x60) & 0xff00);
 141                 outl(((on << 1) + 0x10), (pm10_bar + 0x10));
 142                 dword = inl(pm10_bar + 0x10);
 143                 on = 8 - on;
 144                 printk_debug("Throttling CPU %2d.%1.1d percent.\n",
 145                              (on * 12) + (on >> 1), (on & 1) * 5);
 146         }
 147 #if 0
 148 // default is enabled
 149         /* Enable Port 92 fast reset. */
 150         byte = pci_read_config8(dev, 0xe8);
 151         byte |= ~(1 << 3);
 152         pci_write_config8(dev, 0xe8, byte);
 153 #endif
 154
 155         /* Enable Error reporting. */
 156         /* Set up sync flood detected. */
 157         byte = pci_read_config8(dev, 0x47);
 158         byte |= (1 << 1);
 159         pci_write_config8(dev, 0x47, byte);
 160
 161         /* Set up NMI on errors. */
 162         byte = inb(0x70);               /* RTC70 */
 163         byte_old = byte;
 164         nmi_option = NMI_OFF;
 165         get_option(&nmi_option, "nmi");
 166         if (nmi_option) {
 167                 byte &= ~(1 << 7); /* Set NMI. */
 168         } else {
 169                 byte |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW. */
 170         }
 171         if (byte != byte_old)
 172                 outb(byte, 0x70);
 173
 174         /* Initialize the real time clock (RTC). */
 175         rtc_init(0);
 176
 177         /* Initialize ISA DMA. */
 178         isa_dma_init();
 179
 180         /* Initialize the High Precision Event Timers (HPET). */
 181         enable_hpet(dev);
 182
 183         rom_dummy_write(dev);
 184 }
 185
 186 static void ck804_lpc_read_resources(device_t dev)
 187 {
 188         struct resource *res;
 189         unsigned long index;
 190
 191         /* Get the normal PCI resources of this device. */
 192         /* We got one for APIC, or one more for TRAP. */
 193         pci_dev_read_resources(dev);
 194
 195         /* Get resource for ACPI, SYSTEM_CONTROL, ANALOG_CONTROL. */
 196         for (index = 0x60; index <= 0x68; index += 4)   /* We got another 3. */
 197                 pci_get_resource(dev, index);
 198         compact_resources(dev);
 199
 200         /* Add an extra subtractive resource for both memory and I/O. */
 201         res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
 202         res->base = 0;
 203         res->size = 0x1000;
 204         res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
 205                      IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 206
 207         res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
 208         res->base = 0xff800000;
 209         res->size = 0x00800000; /* 8 MB for flash */
 210         res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
 211                      IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 212
 213         res = new_resource(dev, 3); /* IOAPIC */
 214         res->base = 0xfec00000;
 215         res->size = 0x00001000;
 216         res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 217 }
 218
 219 /**
 220  * Enable resources for children devices.
 221  *
 222  * This function is called by the global enable_resources() indirectly via the
 223  * device_operation::enable_resources() method of devices.
 224  *
 225  * Indirect mutual recursion:
 226  *      enable_childrens_resources() -> enable_resources()
 227  *      enable_resources() -> device_operation::enable_resources()
 228  *      device_operation::enable_resources() -> enable_children_resources()
 229  *
 230  * @param dev The device whose children's resources are to be enabled.
 231  */
 232 static void ck804_lpc_enable_childrens_resources(device_t dev)
 233 {
 234         unsigned link;
 235         uint32_t reg, reg_var[4];
 236         int i, var_num = 0;
 237
 238         reg = pci_read_config32(dev, 0xa0);
 239
 240         for (link = 0; link < dev->links; link++) {
 241                 device_t child;
 242                 for (child = dev->link[link].children; child; child = child->sibling) {
 243                         enable_resources(child);
 244                         if (child->enabled && (child->path.type == DEVICE_PATH_PNP)) {
 245                                 for (i = 0; i < child->resources; i++) {
 246                                         struct resource *res;
 247                                         unsigned long base, end;        // don't need long long
 248                                         res = &child->resource[i];
 249                                         if (!(res->flags & IORESOURCE_IO))
 250                                                 continue;
 251                                         base = res->base;
 252                                         end = resource_end(res);
 253                                         printk_debug("ck804 lpc decode:%s, base=0x%08lx, end=0x%08lx\r\n", dev_path(child), base, end);
 254                                         switch (base) {
 255                                         case 0x3f8:     // COM1
 256                                                 reg |= (1 << 0);
 257                                                 break;
 258                                         case 0x2f8:     // COM2
 259                                                 reg |= (1 << 1);
 260                                                 break;
 261                                         case 0x378:     // Parallel 1
 262                                                 reg |= (1 << 24);
 263                                                 break;
 264                                         case 0x3f0:     // FD0
 265                                                 reg |= (1 << 20);
 266                                                 break;
 267                                         case 0x220:     // Audio 0
 268                                                 reg |= (1 << 8);
 269                                                 break;
 270                                         case 0x300:     // Midi 0
 271                                                 reg |= (1 << 12);
 272                                                 break;
 273                                         }
 274                                         if (base == 0x290 || base >= 0x400) {
 275                                                 if (var_num >= 4)
 276                                                         continue;       // only 4 var ; compact them ?
 277                                                 reg |= (1 << (28 + var_num));
 278                                                 reg_var[var_num++] = (base & 0xffff) | ((end & 0xffff) << 16);
 279                                         }
 280                                 }
 281                         }
 282                 }
 283         }
 284         pci_write_config32(dev, 0xa0, reg);
 285         for (i = 0; i < var_num; i++)
 286                 pci_write_config32(dev, 0xa8 + i * 4, reg_var[i]);
 287 }
 288
 289 static void ck804_lpc_enable_resources(device_t dev)
 290 {
 291         pci_dev_enable_resources(dev);
 292         ck804_lpc_enable_childrens_resources(dev);
 293 }
 294
 295 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 296 {
 297         pci_write_config32(dev, 0x40,
 298                            ((device & 0xffff) << 16) | (vendor & 0xffff));
 299 }
 300
 301 static struct pci_operations lops_pci = {
 302         .set_subsystem = lpci_set_subsystem,
 303 };
 304
 305 static struct device_operations lpc_ops = {
 306         .read_resources   = ck804_lpc_read_resources,
 307         .set_resources    = pci_dev_set_resources,
 308         .enable_resources = ck804_lpc_enable_resources,
 309         .init             = lpc_init,
 310         .scan_bus         = scan_static_bus,
 311         // .enable        = ck804_enable,
 312         .ops_pci          = &lops_pci,
 313 };
 314
 315 static const struct pci_driver lpc_driver __pci_driver = {
 316         .ops    = &lpc_ops,
 317         .vendor = PCI_VENDOR_ID_NVIDIA,
 318         .device = PCI_DEVICE_ID_NVIDIA_CK804_LPC,
 319 };
 320
 321 static const struct pci_driver lpc_driver_pro __pci_driver = {
 322         .ops    = &lpc_ops,
 323         .vendor = PCI_VENDOR_ID_NVIDIA,
 324         .device = PCI_DEVICE_ID_NVIDIA_CK804_PRO,
 325 };
 326
 327 #if CK804_CHIP_REV == 1
 328 static const struct pci_driver lpc_driver_slave __pci_driver = {
 329         .ops    = &lpc_ops,
 330         .vendor = PCI_VENDOR_ID_NVIDIA,
 331         .device = PCI_DEVICE_ID_NVIDIA_CK804_SLAVE,
 332 };
 333 #else
 334 static struct device_operations lpc_slave_ops = {
 335         .read_resources   = ck804_lpc_read_resources,
 336         .set_resources    = pci_dev_set_resources,
 337         .enable_resources = pci_dev_enable_resources,
 338         .init             = lpc_slave_init,
 339         // .enable        = ck804_enable,
 340         .ops_pci          = &lops_pci,
 341 };
 342
 343 static const struct pci_driver lpc_driver_slave __pci_driver = {
 344         .ops    = &lpc_slave_ops,
 345         .vendor = PCI_VENDOR_ID_NVIDIA,
 346         .device = PCI_DEVICE_ID_NVIDIA_CK804_SLAVE,
 347 };
 348 #endif