2 * This file is part of the coreboot project.
4 * Copyright (C) 2008-2009 coresystems GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
23 #include <arch/romcc_io.h>
24 #include <console/console.h>
25 #include <cpu/x86/cache.h>
26 #include <cpu/x86/smm.h>
33 #define ACPI_DISABLE 0x1e
34 #define ACPI_ENABLE 0xe1
38 #define D_OPEN (1 << 6)
39 #define D_CLS (1 << 5)
40 #define D_LCK (1 << 4)
41 #define G_SMRANE (1 << 3)
42 #define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
53 #define PM2_CNT 0x20 // mobile only
57 #define EL_SMI_EN (1 << 25) // Intel Quick Resume Technology
58 #define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic
59 #define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic
60 #define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS
61 #define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al)
62 #define MCSMI_EN (1 << 11) // Trap microcontroller range access
63 #define BIOS_RLS (1 << 7) // asserts SCI on bit set
64 #define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set
65 #define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI#
66 #define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI#
67 #define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic
68 #define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit
69 #define EOS (1 << 1) // End of SMI (deassert SMI#)
70 #define GBL_SMI_EN (1 << 0) // SMI# generation at all?
72 #define ALT_GP_SMI_EN 0x38
73 #define ALT_GP_SMI_STS 0x3a
75 #define DEVACT_STS 0x44
79 //#include "i82801gx_nvs.h"
81 /* While we read PMBASE dynamically in case it changed, let's
82 * initialize it with a sane value
84 static u16 pmbase = DEFAULT_PMBASE;
86 // disabled because SMM doesn't actually work yet
89 * @brief read and clear PM1_STS
90 * @return PM1_STS register
92 static u16 reset_pm1_status(void)
96 reg16 = inw(pmbase + PM1_STS);
97 /* set status bits are cleared by writing 1 to them */
98 outw(reg16, pmbase + PM1_STS);
103 static void dump_pm1_status(u16 pm1_sts)
105 printk(BIOS_DEBUG, "PM1_STS: ");
106 if (pm1_sts & (1 << 15)) printk(BIOS_DEBUG, "WAK ");
107 if (pm1_sts & (1 << 14)) printk(BIOS_DEBUG, "PCIEXPWAK ");
108 if (pm1_sts & (1 << 11)) printk(BIOS_DEBUG, "PRBTNOR ");
109 if (pm1_sts & (1 << 10)) printk(BIOS_DEBUG, "RTC ");
110 if (pm1_sts & (1 << 8)) printk(BIOS_DEBUG, "PWRBTN ");
111 if (pm1_sts & (1 << 5)) printk(BIOS_DEBUG, "GBL ");
112 if (pm1_sts & (1 << 4)) printk(BIOS_DEBUG, "BM ");
113 if (pm1_sts & (1 << 0)) printk(BIOS_DEBUG, "TMROF ");
114 printk(BIOS_DEBUG, "\n");
118 * @brief read and clear SMI_STS
119 * @return SMI_STS register
121 static u32 reset_smi_status(void)
125 reg32 = inl(pmbase + SMI_STS);
126 /* set status bits are cleared by writing 1 to them */
127 outl(reg32, pmbase + SMI_STS);
132 static void dump_smi_status(u32 smi_sts)
134 printk(BIOS_DEBUG, "SMI_STS: ");
135 if (smi_sts & (1 << 26)) printk(BIOS_DEBUG, "SPI ");
136 if (smi_sts & (1 << 25)) printk(BIOS_DEBUG, "EL_SMI ");
137 if (smi_sts & (1 << 21)) printk(BIOS_DEBUG, "MONITOR ");
138 if (smi_sts & (1 << 20)) printk(BIOS_DEBUG, "PCI_EXP_SMI ");
139 if (smi_sts & (1 << 18)) printk(BIOS_DEBUG, "INTEL_USB2 ");
140 if (smi_sts & (1 << 17)) printk(BIOS_DEBUG, "LEGACY_USB2 ");
141 if (smi_sts & (1 << 16)) printk(BIOS_DEBUG, "SMBUS_SMI ");
142 if (smi_sts & (1 << 15)) printk(BIOS_DEBUG, "SERIRQ_SMI ");
143 if (smi_sts & (1 << 14)) printk(BIOS_DEBUG, "PERIODIC ");
144 if (smi_sts & (1 << 13)) printk(BIOS_DEBUG, "TCO ");
145 if (smi_sts & (1 << 12)) printk(BIOS_DEBUG, "DEVMON ");
146 if (smi_sts & (1 << 11)) printk(BIOS_DEBUG, "MCSMI ");
147 if (smi_sts & (1 << 10)) printk(BIOS_DEBUG, "GPI ");
148 if (smi_sts & (1 << 9)) printk(BIOS_DEBUG, "GPE0 ");
149 if (smi_sts & (1 << 8)) printk(BIOS_DEBUG, "PM1 ");
150 if (smi_sts & (1 << 6)) printk(BIOS_DEBUG, "SWSMI_TMR ");
151 if (smi_sts & (1 << 5)) printk(BIOS_DEBUG, "APM ");
152 if (smi_sts & (1 << 4)) printk(BIOS_DEBUG, "SLP_SMI ");
153 if (smi_sts & (1 << 3)) printk(BIOS_DEBUG, "LEGACY_USB ");
154 if (smi_sts & (1 << 2)) printk(BIOS_DEBUG, "BIOS ");
155 printk(BIOS_DEBUG, "\n");
160 * @brief read and clear GPE0_STS
161 * @return GPE0_STS register
163 static u32 reset_gpe0_status(void)
167 reg32 = inl(pmbase + GPE0_STS);
168 /* set status bits are cleared by writing 1 to them */
169 outl(reg32, pmbase + GPE0_STS);
174 static void dump_gpe0_status(u32 gpe0_sts)
177 printk(BIOS_DEBUG, "GPE0_STS: ");
178 for (i=31; i<= 16; i--) {
179 if (gpe0_sts & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", (i-16));
181 if (gpe0_sts & (1 << 14)) printk(BIOS_DEBUG, "USB4 ");
182 if (gpe0_sts & (1 << 13)) printk(BIOS_DEBUG, "PME_B0 ");
183 if (gpe0_sts & (1 << 12)) printk(BIOS_DEBUG, "USB3 ");
184 if (gpe0_sts & (1 << 11)) printk(BIOS_DEBUG, "PME ");
185 if (gpe0_sts & (1 << 10)) printk(BIOS_DEBUG, "EL_SCI/BATLOW ");
186 if (gpe0_sts & (1 << 9)) printk(BIOS_DEBUG, "PCI_EXP ");
187 if (gpe0_sts & (1 << 8)) printk(BIOS_DEBUG, "RI ");
188 if (gpe0_sts & (1 << 7)) printk(BIOS_DEBUG, "SMB_WAK ");
189 if (gpe0_sts & (1 << 6)) printk(BIOS_DEBUG, "TCO_SCI ");
190 if (gpe0_sts & (1 << 5)) printk(BIOS_DEBUG, "AC97 ");
191 if (gpe0_sts & (1 << 4)) printk(BIOS_DEBUG, "USB2 ");
192 if (gpe0_sts & (1 << 3)) printk(BIOS_DEBUG, "USB1 ");
193 if (gpe0_sts & (1 << 2)) printk(BIOS_DEBUG, "HOT_PLUG ");
194 if (gpe0_sts & (1 << 0)) printk(BIOS_DEBUG, "THRM ");
195 printk(BIOS_DEBUG, "\n");
200 * @brief read and clear TCOx_STS
201 * @return TCOx_STS registers
203 static u32 reset_tco_status(void)
205 u32 tcobase = pmbase + 0x60;
208 reg32 = inl(tcobase + 0x04);
209 /* set status bits are cleared by writing 1 to them */
210 outl(reg32 & ~(1<<18), tcobase + 0x04); // Don't clear BOOT_STS before SECOND_TO_STS
211 if (reg32 & (1 << 18))
212 outl(reg32 & (1<<18), tcobase + 0x04); // clear BOOT_STS
218 static void dump_tco_status(u32 tco_sts)
220 printk(BIOS_DEBUG, "TCO_STS: ");
221 if (tco_sts & (1 << 20)) printk(BIOS_DEBUG, "SMLINK_SLV ");
222 if (tco_sts & (1 << 18)) printk(BIOS_DEBUG, "BOOT ");
223 if (tco_sts & (1 << 17)) printk(BIOS_DEBUG, "SECOND_TO ");
224 if (tco_sts & (1 << 16)) printk(BIOS_DEBUG, "INTRD_DET ");
225 if (tco_sts & (1 << 12)) printk(BIOS_DEBUG, "DMISERR ");
226 if (tco_sts & (1 << 10)) printk(BIOS_DEBUG, "DMISMI ");
227 if (tco_sts & (1 << 9)) printk(BIOS_DEBUG, "DMISCI ");
228 if (tco_sts & (1 << 8)) printk(BIOS_DEBUG, "BIOSWR ");
229 if (tco_sts & (1 << 7)) printk(BIOS_DEBUG, "NEWCENTURY ");
230 if (tco_sts & (1 << 3)) printk(BIOS_DEBUG, "TIMEOUT ");
231 if (tco_sts & (1 << 2)) printk(BIOS_DEBUG, "TCO_INT ");
232 if (tco_sts & (1 << 1)) printk(BIOS_DEBUG, "SW_TCO ");
233 if (tco_sts & (1 << 0)) printk(BIOS_DEBUG, "NMI2SMI ");
234 printk(BIOS_DEBUG, "\n");
239 /* We are using PCIe accesses for now
240 * 1. the chipset can do it
241 * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind
243 //#include "../../../northbridge/intel/i945/pcie_config.c"
245 int southbridge_io_trap_handler(int smif)
247 //global_nvs_t *gnvs = (global_nvs_t *)0xc00;
251 printk(BIOS_DEBUG, "OS Init\n");
259 /* On success, the IO Trap Handler returns 0
260 * On failure, the IO Trap Handler returns a value != 0
262 * For now, we force the return value to 0 and log all traps to
263 * see what's going on.
266 return 1; /* IO trap handled */
270 * @brief Set the EOS bit
272 void southbridge_smi_set_eos(void)
276 reg8 = inb(pmbase + SMI_EN);
278 outb(reg8, pmbase + SMI_EN);
282 * @brief Interrupt handler for SMI#
284 * @param smm_revision revision of the smm state save map
287 void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save)
289 // FIXME: the necessary magic isn't available yet. the code
290 // below is a partially adapted ICH7 version of the handler
295 u32 smi_sts, gpe0_sts, tco_sts;
297 pmbase = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0x48) & 0xfffc;
298 printk(BIOS_SPEW, "SMI#: pmbase = 0x%04x\n", pmbase);
300 /* We need to clear the SMI status registers, or we won't see what's
301 * happening in the following calls.
303 smi_sts = reset_smi_status();
304 dump_smi_status(smi_sts);
306 if (smi_sts & (1 << 21)) { // MONITOR
307 global_nvs_t *gnvs = (global_nvs_t *)0xc00;
310 reg32 = RCBA32(0x1e00); TRSR - Trap Status Register
312 /* Comment in for some useful debug */
313 for (i=0; i<4; i++) {
314 if (reg32 & (1 << i)) {
315 printk(BIOS_DEBUG, " io trap #%d\n", i);
319 RCBA32(0x1e00) = reg32; TRSR
321 reg32 = RCBA32(0x1e10);
323 if ((reg32 & 0xfffc) != 0x808) {
324 printk(BIOS_DEBUG, " trapped io address = 0x%x\n", reg32 & 0xfffc);
325 printk(BIOS_DEBUG, " AHBE = %x\n", (reg32 >> 16) & 0xf);
326 printk(BIOS_DEBUG, " read/write: %s\n", (reg32 & (1 << 24)) ? "read" :
330 if (!(reg32 & (1 << 24))) {
332 reg32 = RCBA32(0x1e18);
333 printk(BIOS_DEBUG, " iotrap written data = 0x%08x\n", reg32);
338 io_trap_handler(gnvs->smif); // call function smif
341 if (smi_sts & (1 << 13)) { // TCO
342 tco_sts = reset_tco_status();
343 dump_tco_status(tco_sts);
345 if (tco_sts & (1 << 8)) { // BIOSWR
347 bios_cntl = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc);
349 /* BWE is RW, so the SMI was caused by a
350 * write to BWE, not by a write to the BIOS
353 /* This is the place where we notice someone
354 * is trying to tinker with the BIOS. We are
355 * trying to be nice and just ignore it. A more
356 * resolute answer would be to power down the
359 printk(BIOS_DEBUG, "Switching back to RO\n");
360 pcie_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1));
361 } /* No else for now? */
365 if (smi_sts & (1 << 8)) { // PM1
366 pm1_sts = reset_pm1_status();
367 dump_pm1_status(pm1_sts);
370 if (smi_sts & (1 << 9)) { // GPE0
371 gpe0_sts = reset_gpe0_status();
372 dump_gpe0_status(gpe0_sts);
375 if (smi_sts & (1 << 5)) { // APM
376 /* Emulate B2 register as the FADT / Linux expects it */
381 pmctrl = inw(pmbase + 0x04);
383 outw(pmctrl, pmbase + 0x04);
384 printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n");
387 pmctrl = inw(pmbase + 0x04);
389 outw(pmctrl, pmbase + 0x04);
390 printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n");
395 if (smi_sts & (1 << 4)) { // SLP_SMI
398 /* First, disable further SMIs */
399 reg8 = inb(pmbase + SMI_EN);
401 outb(reg8, pmbase + SMI_EN);
403 /* Next, do the deed, we should change
404 * power on after power loss bits here
405 * if we're going to S5
408 /* Write back to the SLP register to cause the
409 * originally intended event again. We need to set BIT13
410 * (SLP_EN) though to make the sleep happen.
412 reg32 = inl(pmbase + 0x04);
413 printk(BIOS_DEBUG, "SMI#: SLP = 0x%08x\n", reg32);
414 printk(BIOS_DEBUG, "SMI#: Powering off.\n");
415 outl(reg32 | (1 << 13), pmbase + 0x04);