2 * (C) 2003-2004 Linux Networx
4 #include <console/console.h>
5 #include <device/device.h>
6 #include <device/pci.h>
7 #include <device/pci_ids.h>
8 #include <device/pci_ops.h>
9 #include <device/pcix.h>
10 #include <pc80/mc146818rtc.h>
11 #include <arch/ioapic.h>
15 static void pxhd_enable(device_t dev)
19 if ((dev->path.pci.devfn & 1) == 0) {
20 /* Can we enable/disable the bridges? */
23 bridge = dev_find_slot(dev->bus->secondary, dev->path.pci.devfn & ~1);
25 printk(BIOS_ERR, "Cannot find bridge for ioapic: %s\n",
29 value = pci_read_config16(bridge, 0x40);
34 pci_write_config16(bridge, 0x40, value);
40 static unsigned int pxhd_scan_bridge(device_t dev, unsigned int max)
44 dev->link[0].dev = dev;
47 get_option(&bus_100Mhz, "pxhd_bus_speed_100");
51 printk(BIOS_DEBUG, "setting pxhd bus to 100 Mhz\n");
52 /* set to pcix 100 mhz */
53 word = pci_read_config16(dev, 0x40);
58 pci_write_config16(dev, 0x40, word);
60 /* reset the bus to make the new frequencies effective */
61 pci_bus_reset(&dev->link[0]);
63 return pcix_scan_bridge(dev, max);
65 static void pcix_init(device_t dev)
67 /* Bridge control ISA enable */
68 pci_write_config8(dev, 0x3e, 0x07);
70 #warning "Please review lots of dead code here."
77 /* Enable memory write and invalidate ??? */
78 byte = pci_read_config8(dev, 0x04);
80 pci_write_config8(dev, 0x04, byte);
82 /* Set drive strength */
83 word = pci_read_config16(dev, 0xe0);
85 pci_write_config16(dev, 0xe0, word);
86 word = pci_read_config16(dev, 0xe4);
88 pci_write_config16(dev, 0xe4, word);
91 word = pci_read_config16(dev, 0xe8);
93 pci_write_config16(dev, 0xe8, word);
95 /* Set discard unrequested prefetch data */
96 word = pci_read_config16(dev, 0x4c);
98 pci_write_config16(dev, 0x4c, word);
100 /* Set split transaction limits */
101 word = pci_read_config16(dev, 0xa8);
102 pci_write_config16(dev, 0xaa, word);
103 word = pci_read_config16(dev, 0xac);
104 pci_write_config16(dev, 0xae, word);
106 /* Set up error reporting, enable all */
107 /* system error enable */
108 dword = pci_read_config32(dev, 0x04);
110 pci_write_config32(dev, 0x04, dword);
112 /* system and error parity enable */
113 dword = pci_read_config32(dev, 0x3c);
115 pci_write_config32(dev, 0x3c, dword);
118 nmi_option = NMI_OFF;
119 get_option(&nmi_option, "nmi");
121 dword = pci_read_config32(dev, 0x44);
123 pci_write_config32(dev, 0x44, dword);
126 /* Set up CRC flood enable */
127 dword = pci_read_config32(dev, 0xc0);
128 if(dword) { /* do device A only */
129 dword = pci_read_config32(dev, 0xc4);
131 pci_write_config32(dev, 0xc4, dword);
132 dword = pci_read_config32(dev, 0xc8);
134 pci_write_config32(dev, 0xc8, dword);
141 static struct device_operations pcix_ops = {
142 .read_resources = pci_bus_read_resources,
143 .set_resources = pci_dev_set_resources,
144 .enable_resources = pci_bus_enable_resources,
146 .scan_bus = pxhd_scan_bridge,
147 .reset_bus = pci_bus_reset,
151 static const struct pci_driver pcix_driver __pci_driver = {
153 .vendor = PCI_VENDOR_ID_INTEL,
157 static const struct pci_driver pcix_driver2 __pci_driver = {
159 .vendor = PCI_VENDOR_ID_INTEL,
163 static void ioapic_init(device_t dev)
165 uint32_t value, ioapic_base;
166 /* Enable bus mastering so IOAPICs work */
167 value = pci_read_config16(dev, PCI_COMMAND);
168 value |= PCI_COMMAND_MASTER;
169 pci_write_config16(dev, PCI_COMMAND, value);
171 ioapic_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
173 setup_ioapic(ioapic_base, 0); // Don't rename IOAPIC ID
176 static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device)
178 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
179 ((device & 0xffff) << 16) | (vendor & 0xffff));
182 static struct pci_operations intel_ops_pci = {
183 .set_subsystem = intel_set_subsystem,
186 static struct device_operations ioapic_ops = {
187 .read_resources = pci_dev_read_resources,
188 .set_resources = pci_dev_set_resources,
189 .enable_resources = pci_dev_enable_resources,
192 .enable = pxhd_enable,
193 .ops_pci = &intel_ops_pci,
196 static const struct pci_driver ioapic_driver __pci_driver = {
198 .vendor = PCI_VENDOR_ID_INTEL,
203 static const struct pci_driver ioapic2_driver __pci_driver = {
205 .vendor = PCI_VENDOR_ID_INTEL,
210 struct chip_operations southbridge_intel_pxhd_ops = {
211 CHIP_NAME("Intel PXHD Southbridge")
212 .enable_dev = pxhd_enable,