2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #ifndef SOUTHBRIDGE_INTEL_I82801XX_I82801XX_H
22 #define SOUTHBRIDGE_INTEL_I82801XX_I82801XX_H
26 extern void i82801xx_enable(device_t dev);
29 #define PCI_DMA_CFG 0x90
30 #define SERIRQ_CNTL 0x64
34 #define GEN_PMCON_3 0xa4
37 #define ACPI_CNTL 0x44
38 #define BIOS_CNTL 0x4E
39 #define GPIO_BASE_ICH0_5 0x58 /* LPC GPIO Base Addr. Reg. (ICH0-ICH5) */
40 #define GPIO_BASE_ICH6_9 0x48 /* LPC GPIO Base Address Register (ICH6-ICH9) */
41 #define GPIO_CNTL_ICH0_5 0x5C /* LPC GPIO Control Register (ICH0-ICH5) */
42 #define GPIO_CNTL_ICH6_9 0x4C /* LPC GPIO Control Register (ICH6-ICH9) */
44 #define PIRQA_ROUT 0x60
45 #define PIRQB_ROUT 0x61
46 #define PIRQC_ROUT 0x62
47 #define PIRQD_ROUT 0x63
48 #define PIRQE_ROUT 0x68
49 #define PIRQF_ROUT 0x69
50 #define PIRQG_ROUT 0x6A
51 #define PIRQH_ROUT 0x6B
55 #define COM_DEC 0xE0 /* LPC I/F Communication Port Decode Ranges (ICH0-ICH5) */
56 #define LPC_IO_DEC 0x80 /* IO Decode Ranges Register (ICH6-ICH9) */
57 #define LPC_EN_ICH0_5 0xE6 /* LPC IF Enables Register (ICH0-ICH5) */
58 #define LPC_EN_ICH6_9 0x82 /* LPC IF Enables Register (ICH6-ICH9) */
61 #define SUB_BUS_NUM 0x1A
69 #define PCI_MAST_STS 0x82
71 /* GEN_PMCON_3 bits */
72 #define RTC_BATTERY_DEAD (1 << 2)
73 #define RTC_POWER_FAILED (1 << 1)
74 #define SLEEP_AFTER_POWER_FAIL (1 << 0)
76 /* PCI Configuration Space (D31:F1) */
77 #define IDE_TIM_PRI 0x40 /* IDE timings, primary */
78 #define IDE_TIM_SEC 0x42 /* IDE timings, secondary */
81 #define IDE_DECODE_ENABLE (1 << 15)
83 /* PCI Configuration Space (D31:F3) */
88 #define I2C_EN (1 << 2)
89 #define SMB_SMI_EN (1 << 1)
90 #define HST_EN (1 << 0)
93 * TODO: Does it matter where we put the SMBus IO base, as long as we keep
94 * consistent and don't interfere with anything else?
96 /* #define SMBUS_IO_BASE 0x1000 */
97 #define SMBUS_IO_BASE 0x0f00
99 #define SMBHSTSTAT 0x0
100 #define SMBHSTCTL 0x2
101 #define SMBHSTCMD 0x3
102 #define SMBXMITADD 0x4
103 #define SMBHSTDAT0 0x5
104 #define SMBHSTDAT1 0x6
105 #define SMBBLKDAT 0x7
106 #define SMBTRNSADD 0x9
107 #define SMBSLVDATA 0xa
108 #define SMLINK_PIN_CTL 0xe
109 #define SMBUS_PIN_CTL 0xf
111 #define SMBUS_TIMEOUT (10 * 1000 * 100)
113 /* HPET, if present */
114 #define HPET_ADDR 0xfed0000
116 #endif /* SOUTHBRIDGE_INTEL_I82801XX_I82801XX_H */