2 * This file is part of the coreboot project.
4 * Copyright (C) 2008-2009 coresystems GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
24 #include <arch/romcc_io.h>
25 #include <console/console.h>
26 #include <cpu/x86/cache.h>
27 #include <cpu/x86/smm.h>
28 #include <device/pci_def.h>
29 #include <pc80/mc146818rtc.h>
34 #define D_OPEN (1 << 6)
35 #define D_CLS (1 << 5)
36 #define D_LCK (1 << 4)
37 #define G_SMRANE (1 << 3)
38 #define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
42 /* While we read PMBASE dynamically in case it changed, let's
43 * initialize it with a sane value
45 u16 pmbase = DEFAULT_PMBASE;
46 u8 smm_initialized = 0;
48 /* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located
51 global_nvs_t *gnvs = (global_nvs_t *)0x0;
52 void *tcg = (void *)0x0;
53 void *smi1 = (void *)0x0;
56 * @brief read and clear PM1_STS
57 * @return PM1_STS register
59 static u16 reset_pm1_status(void)
63 reg16 = inw(pmbase + PM1_STS);
64 /* set status bits are cleared by writing 1 to them */
65 outw(reg16, pmbase + PM1_STS);
70 static void dump_pm1_status(u16 pm1_sts)
72 printk(BIOS_SPEW, "PM1_STS: ");
73 if (pm1_sts & (1 << 15)) printk(BIOS_SPEW, "WAK ");
74 if (pm1_sts & (1 << 14)) printk(BIOS_SPEW, "PCIEXPWAK ");
75 if (pm1_sts & (1 << 11)) printk(BIOS_SPEW, "PRBTNOR ");
76 if (pm1_sts & (1 << 10)) printk(BIOS_SPEW, "RTC ");
77 if (pm1_sts & (1 << 8)) printk(BIOS_SPEW, "PWRBTN ");
78 if (pm1_sts & (1 << 5)) printk(BIOS_SPEW, "GBL ");
79 if (pm1_sts & (1 << 4)) printk(BIOS_SPEW, "BM ");
80 if (pm1_sts & (1 << 0)) printk(BIOS_SPEW, "TMROF ");
81 printk(BIOS_SPEW, "\n");
82 int reg16 = inw(pmbase + PM1_EN);
83 printk(BIOS_SPEW, "PM1_EN: %x\n", reg16);
87 * @brief read and clear SMI_STS
88 * @return SMI_STS register
90 static u32 reset_smi_status(void)
94 reg32 = inl(pmbase + SMI_STS);
95 /* set status bits are cleared by writing 1 to them */
96 outl(reg32, pmbase + SMI_STS);
101 static void dump_smi_status(u32 smi_sts)
103 printk(BIOS_DEBUG, "SMI_STS: ");
104 if (smi_sts & (1 << 26)) printk(BIOS_DEBUG, "SPI ");
105 if (smi_sts & (1 << 25)) printk(BIOS_DEBUG, "EL_SMI ");
106 if (smi_sts & (1 << 21)) printk(BIOS_DEBUG, "MONITOR ");
107 if (smi_sts & (1 << 20)) printk(BIOS_DEBUG, "PCI_EXP_SMI ");
108 if (smi_sts & (1 << 18)) printk(BIOS_DEBUG, "INTEL_USB2 ");
109 if (smi_sts & (1 << 17)) printk(BIOS_DEBUG, "LEGACY_USB2 ");
110 if (smi_sts & (1 << 16)) printk(BIOS_DEBUG, "SMBUS_SMI ");
111 if (smi_sts & (1 << 15)) printk(BIOS_DEBUG, "SERIRQ_SMI ");
112 if (smi_sts & (1 << 14)) printk(BIOS_DEBUG, "PERIODIC ");
113 if (smi_sts & (1 << 13)) printk(BIOS_DEBUG, "TCO ");
114 if (smi_sts & (1 << 12)) printk(BIOS_DEBUG, "DEVMON ");
115 if (smi_sts & (1 << 11)) printk(BIOS_DEBUG, "MCSMI ");
116 if (smi_sts & (1 << 10)) printk(BIOS_DEBUG, "GPI ");
117 if (smi_sts & (1 << 9)) printk(BIOS_DEBUG, "GPE0 ");
118 if (smi_sts & (1 << 8)) printk(BIOS_DEBUG, "PM1 ");
119 if (smi_sts & (1 << 6)) printk(BIOS_DEBUG, "SWSMI_TMR ");
120 if (smi_sts & (1 << 5)) printk(BIOS_DEBUG, "APM ");
121 if (smi_sts & (1 << 4)) printk(BIOS_DEBUG, "SLP_SMI ");
122 if (smi_sts & (1 << 3)) printk(BIOS_DEBUG, "LEGACY_USB ");
123 if (smi_sts & (1 << 2)) printk(BIOS_DEBUG, "BIOS ");
124 printk(BIOS_DEBUG, "\n");
129 * @brief read and clear GPE0_STS
130 * @return GPE0_STS register
132 static u32 reset_gpe0_status(void)
136 reg32 = inl(pmbase + GPE0_STS);
137 /* set status bits are cleared by writing 1 to them */
138 outl(reg32, pmbase + GPE0_STS);
143 static void dump_gpe0_status(u32 gpe0_sts)
146 printk(BIOS_DEBUG, "GPE0_STS: ");
147 for (i=31; i<= 16; i--) {
148 if (gpe0_sts & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", (i-16));
150 if (gpe0_sts & (1 << 14)) printk(BIOS_DEBUG, "USB4 ");
151 if (gpe0_sts & (1 << 13)) printk(BIOS_DEBUG, "PME_B0 ");
152 if (gpe0_sts & (1 << 12)) printk(BIOS_DEBUG, "USB3 ");
153 if (gpe0_sts & (1 << 11)) printk(BIOS_DEBUG, "PME ");
154 if (gpe0_sts & (1 << 10)) printk(BIOS_DEBUG, "EL_SCI/BATLOW ");
155 if (gpe0_sts & (1 << 9)) printk(BIOS_DEBUG, "PCI_EXP ");
156 if (gpe0_sts & (1 << 8)) printk(BIOS_DEBUG, "RI ");
157 if (gpe0_sts & (1 << 7)) printk(BIOS_DEBUG, "SMB_WAK ");
158 if (gpe0_sts & (1 << 6)) printk(BIOS_DEBUG, "TCO_SCI ");
159 if (gpe0_sts & (1 << 5)) printk(BIOS_DEBUG, "AC97 ");
160 if (gpe0_sts & (1 << 4)) printk(BIOS_DEBUG, "USB2 ");
161 if (gpe0_sts & (1 << 3)) printk(BIOS_DEBUG, "USB1 ");
162 if (gpe0_sts & (1 << 2)) printk(BIOS_DEBUG, "HOT_PLUG ");
163 if (gpe0_sts & (1 << 0)) printk(BIOS_DEBUG, "THRM ");
164 printk(BIOS_DEBUG, "\n");
169 * @brief read and clear TCOx_STS
170 * @return TCOx_STS registers
172 static u32 reset_tco_status(void)
174 u32 tcobase = pmbase + 0x60;
177 reg32 = inl(tcobase + 0x04);
178 /* set status bits are cleared by writing 1 to them */
179 outl(reg32 & ~(1<<18), tcobase + 0x04); // Don't clear BOOT_STS before SECOND_TO_STS
180 if (reg32 & (1 << 18))
181 outl(reg32 & (1<<18), tcobase + 0x04); // clear BOOT_STS
187 static void dump_tco_status(u32 tco_sts)
189 printk(BIOS_DEBUG, "TCO_STS: ");
190 if (tco_sts & (1 << 20)) printk(BIOS_DEBUG, "SMLINK_SLV ");
191 if (tco_sts & (1 << 18)) printk(BIOS_DEBUG, "BOOT ");
192 if (tco_sts & (1 << 17)) printk(BIOS_DEBUG, "SECOND_TO ");
193 if (tco_sts & (1 << 16)) printk(BIOS_DEBUG, "INTRD_DET ");
194 if (tco_sts & (1 << 12)) printk(BIOS_DEBUG, "DMISERR ");
195 if (tco_sts & (1 << 10)) printk(BIOS_DEBUG, "DMISMI ");
196 if (tco_sts & (1 << 9)) printk(BIOS_DEBUG, "DMISCI ");
197 if (tco_sts & (1 << 8)) printk(BIOS_DEBUG, "BIOSWR ");
198 if (tco_sts & (1 << 7)) printk(BIOS_DEBUG, "NEWCENTURY ");
199 if (tco_sts & (1 << 3)) printk(BIOS_DEBUG, "TIMEOUT ");
200 if (tco_sts & (1 << 2)) printk(BIOS_DEBUG, "TCO_INT ");
201 if (tco_sts & (1 << 1)) printk(BIOS_DEBUG, "SW_TCO ");
202 if (tco_sts & (1 << 0)) printk(BIOS_DEBUG, "NMI2SMI ");
203 printk(BIOS_DEBUG, "\n");
206 /* We are using PCIe accesses for now
207 * 1. the chipset can do it
208 * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind
210 #include "../../../northbridge/intel/i945/pcie_config.c"
212 int southbridge_io_trap_handler(int smif)
216 printk(BIOS_DEBUG, "OS Init\n");
218 * On success, the IO Trap Handler returns 0
219 * On failure, the IO Trap Handler returns a value != 0
222 return 1; /* IO trap handled */
230 * @brief Set the EOS bit
232 void southbridge_smi_set_eos(void)
236 reg8 = inb(pmbase + SMI_EN);
238 outb(reg8, pmbase + SMI_EN);
241 static void busmaster_disable_on_bus(int bus)
247 for (slot = 0; slot < 0x20; slot++) {
248 for (func = 0; func < 8; func++) {
250 device_t dev = PCI_DEV(bus, slot, func);
252 val = pci_read_config32(dev, PCI_VENDOR_ID);
254 if (val == 0xffffffff || val == 0x00000000 ||
255 val == 0x0000ffff || val == 0xffff0000)
258 /* Disable Bus Mastering for this one device */
259 reg32 = pci_read_config32(dev, PCI_COMMAND);
260 reg32 &= ~PCI_COMMAND_MASTER;
261 pci_write_config32(dev, PCI_COMMAND, reg32);
263 /* If this is a bridge, then follow it. */
264 hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
266 if (hdr == PCI_HEADER_TYPE_BRIDGE ||
267 hdr == PCI_HEADER_TYPE_CARDBUS) {
269 buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
270 busmaster_disable_on_bus((buses >> 8) & 0xff);
277 static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *state_save)
282 u8 s5pwr = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
284 // save and recover RTC port values
288 get_option(&s5pwr, "power_on_after_fail");
292 /* First, disable further SMIs */
293 reg8 = inb(pmbase + SMI_EN);
295 outb(reg8, pmbase + SMI_EN);
297 /* Figure out SLP_TYP */
298 reg32 = inl(pmbase + PM1_CNT);
299 printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32);
300 slp_typ = (reg32 >> 10) & 7;
302 /* Next, do the deed.
306 case 0: printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n"); break;
307 case 1: printk(BIOS_DEBUG, "SMI#: Entering S1 (Assert STPCLK#)\n"); break;
309 printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n");
310 /* Invalidate the cache before going to S3 */
313 case 6: printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n"); break;
315 printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n");
317 outl(0, pmbase + GPE0_EN);
319 /* Should we keep the power state after a power loss?
320 * In case the setting is "ON" or "OFF" we don't have
321 * to do anything. But if it's "KEEP" we have to switch
322 * to "OFF" before entering S5.
324 if (s5pwr == MAINBOARD_POWER_KEEP) {
325 reg8 = pcie_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
327 pcie_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
330 /* also iterates over all bridges on bus 0 */
331 busmaster_disable_on_bus(0);
333 default: printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n"); break;
336 /* Unlock the SMI semaphore. We're currently in SMM, and the semaphore
337 * will never be unlocked because the next outl will switch off the CPU.
338 * This might open a small race between the smi_release_lock() and the outl()
339 * for other SMI handlers. Not sure if this could cause trouble. */
343 /* Write back to the SLP register to cause the originally intended
344 * event again. We need to set BIT13 (SLP_EN) though to make the
347 outl(reg32 | SLP_EN, pmbase + PM1_CNT);
349 /* In most sleep states, the code flow of this function ends at
350 * the line above. However, if we entered sleep state S1 and wake
351 * up again, we will continue to execute code in this function.
353 reg32 = inl(pmbase + PM1_CNT);
354 if (reg32 & SCI_EN) {
355 /* The OS is not an ACPI OS, so we set the state to S0 */
356 reg32 &= ~(SLP_EN | SLP_TYP);
357 outl(reg32, pmbase + PM1_CNT);
361 static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state_save)
366 /* Emulate B2 register as the FADT / Linux expects it */
369 if (mainboard_apm_cnt && mainboard_apm_cnt(reg8))
373 case APM_CNT_CST_CONTROL:
374 /* Calling this function seems to cause
375 * some kind of race condition in Linux
376 * and causes a kernel oops
378 printk(BIOS_DEBUG, "C-state control\n");
380 case APM_CNT_PST_CONTROL:
381 /* Calling this function seems to cause
382 * some kind of race condition in Linux
383 * and causes a kernel oops
385 printk(BIOS_DEBUG, "P-state control\n");
387 case APM_CNT_ACPI_DISABLE:
388 pmctrl = inl(pmbase + PM1_CNT);
390 outl(pmctrl, pmbase + PM1_CNT);
391 printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n");
393 case APM_CNT_ACPI_ENABLE:
394 pmctrl = inl(pmbase + PM1_CNT);
396 outl(pmctrl, pmbase + PM1_CNT);
397 printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n");
399 case APM_CNT_GNVS_UPDATE:
400 if (smm_initialized) {
401 printk(BIOS_DEBUG, "SMI#: SMM structures already initialized!\n");
404 gnvs = *(global_nvs_t **)0x500;
405 tcg = *(void **)0x504;
406 smi1 = *(void **)0x508;
408 printk(BIOS_DEBUG, "SMI#: Setting up structures to %p, %p, %p\n", gnvs, tcg, smi1);
411 printk(BIOS_DEBUG, "SMI#: Unknown function APM_CNT=%02x\n", reg8);
415 static void southbridge_smi_pm1(unsigned int node, smm_state_save_area_t *state_save)
418 volatile u8 cmos_status;
420 pm1_sts = reset_pm1_status();
421 dump_pm1_status(pm1_sts);
423 /* While OSPM is not active, poweroff immediately
424 * on a power button event.
426 if (pm1_sts & PWRBTN_STS) {
427 // power button pressed
429 reg32 = (7 << 10) | (1 << 13);
430 outl(reg32, pmbase + PM1_CNT);
433 if (pm1_sts & RTC_STS) {
434 /* read RTC status register to disable the interrupt */
435 cmos_status = cmos_read(RTC_REG_C);
436 printk(BIOS_DEBUG, "RTC IRQ status: %02X\n", cmos_status);
440 static void southbridge_smi_gpe0(unsigned int node, smm_state_save_area_t *state_save)
444 gpe0_sts = reset_gpe0_status();
445 dump_gpe0_status(gpe0_sts);
448 static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_save)
451 reg16 = inw(pmbase + ALT_GP_SMI_STS);
452 outl(reg16, pmbase + ALT_GP_SMI_STS);
454 reg16 &= inw(pmbase + ALT_GP_SMI_EN);
456 if (mainboard_smi_gpi) {
457 mainboard_smi_gpi(reg16);
460 printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16);
464 static void southbridge_smi_mc(unsigned int node, smm_state_save_area_t *state_save)
468 reg32 = inl(pmbase + SMI_EN);
470 /* Are periodic SMIs enabled? */
471 if ((reg32 & MCSMI_EN) == 0)
474 printk(BIOS_DEBUG, "Microcontroller SMI.\n");
479 static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_save)
483 tco_sts = reset_tco_status();
489 if (tco_sts & (1 << 8)) { // BIOSWR
492 bios_cntl = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc);
495 /* BWE is RW, so the SMI was caused by a
496 * write to BWE, not by a write to the BIOS
499 /* This is the place where we notice someone
500 * is trying to tinker with the BIOS. We are
501 * trying to be nice and just ignore it. A more
502 * resolute answer would be to power down the
505 printk(BIOS_DEBUG, "Switching back to RO\n");
506 pcie_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1));
507 } /* No else for now? */
508 } else if (tco_sts & (1 << 3)) { /* TIMEOUT */
509 /* Handle TCO timeout */
510 printk(BIOS_DEBUG, "TCO Timeout.\n");
511 } else if (!tco_sts) {
512 dump_tco_status(tco_sts);
516 static void southbridge_smi_periodic(unsigned int node, smm_state_save_area_t *state_save)
520 reg32 = inl(pmbase + SMI_EN);
522 /* Are periodic SMIs enabled? */
523 if ((reg32 & PERIODIC_EN) == 0)
526 printk(BIOS_DEBUG, "Periodic SMI.\n");
529 static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *state_save)
531 #define IOTRAP(x) (trap_sts & (1 << x))
532 u32 trap_sts, trap_cycle;
536 trap_sts = RCBA32(0x1e00); // TRSR - Trap Status Register
537 RCBA32(0x1e00) = trap_sts; // Clear trap(s) in TRSR
539 trap_cycle = RCBA32(0x1e10);
540 for (i=16; i<20; i++) {
541 if (trap_cycle & (1 << i))
542 mask |= (0xff << ((i - 16) << 2));
546 /* IOTRAP(3) SMI function call */
548 if (gnvs && gnvs->smif)
549 io_trap_handler(gnvs->smif); // call function smif
553 /* IOTRAP(2) currently unused
554 * IOTRAP(1) currently unused */
558 if (!(trap_cycle & (1 << 24))) { // It's a write
559 printk(BIOS_DEBUG, "SMI1 command\n");
560 data = RCBA32(0x1e18);
563 // southbridge_smi_command(data);
566 // Fall through to debug
569 printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc);
570 for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAPĀ = %d\n", i);
571 printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf);
572 printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask);
573 printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write");
575 if (!(trap_cycle & (1 << 24))) {
577 data = RCBA32(0x1e18);
578 printk(BIOS_DEBUG, " iotrap written data = 0x%08x\n", data);
583 typedef void (*smi_handler_t)(unsigned int node,
584 smm_state_save_area_t *state_save);
586 smi_handler_t southbridge_smi[32] = {
587 NULL, // [0] reserved
588 NULL, // [1] reserved
589 NULL, // [2] BIOS_STS
590 NULL, // [3] LEGACY_USB_STS
591 southbridge_smi_sleep, // [4] SLP_SMI_STS
592 southbridge_smi_apmc, // [5] APM_STS
593 NULL, // [6] SWSMI_TMR_STS
594 NULL, // [7] reserved
595 southbridge_smi_pm1, // [8] PM1_STS
596 southbridge_smi_gpe0, // [9] GPE0_STS
597 southbridge_smi_gpi, // [10] GPI_STS
598 southbridge_smi_mc, // [11] MCSMI_STS
599 NULL, // [12] DEVMON_STS
600 southbridge_smi_tco, // [13] TCO_STS
601 southbridge_smi_periodic, // [14] PERIODIC_STS
602 NULL, // [15] SERIRQ_SMI_STS
603 NULL, // [16] SMBUS_SMI_STS
604 NULL, // [17] LEGACY_USB2_STS
605 NULL, // [18] INTEL_USB2_STS
606 NULL, // [19] reserved
607 NULL, // [20] PCI_EXP_SMI_STS
608 southbridge_smi_monitor, // [21] MONITOR_STS
609 NULL, // [22] reserved
610 NULL, // [23] reserved
611 NULL, // [24] reserved
612 NULL, // [25] EL_SMI_STS
613 NULL, // [26] SPI_STS
614 NULL, // [27] reserved
615 NULL, // [28] reserved
616 NULL, // [29] reserved
617 NULL, // [30] reserved
618 NULL // [31] reserved
622 * @brief Interrupt handler for SMI#
624 * @param smm_revision revision of the smm state save map
627 void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save)
632 /* Update global variable pmbase */
633 pmbase = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
635 /* We need to clear the SMI status registers, or we won't see what's
636 * happening in the following calls.
638 smi_sts = reset_smi_status();
640 /* Filter all non-enabled SMI events */
641 // FIXME Double check, this clears MONITOR
642 // smi_sts &= inl(pmbase + SMI_EN);
644 /* Call SMI sub handler for each of the status bits */
645 for (i = 0; i < 31; i++) {
646 if (smi_sts & (1 << i)) {
647 if (southbridge_smi[i])
648 southbridge_smi[i](node, state_save);
650 printk(BIOS_DEBUG, "SMI_STS[%d] occured, but no "
651 "handler available.\n", i);
658 dump_smi_status(smi_sts);