2 * This file is part of the coreboot project.
4 * Copyright (C) 2008-2009 coresystems GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
24 #include <arch/romcc_io.h>
25 #include <console/console.h>
26 #include <cpu/x86/cache.h>
27 #include <cpu/x86/smm.h>
28 #include <device/pci_def.h>
33 #define D_OPEN (1 << 6)
34 #define D_CLS (1 << 5)
35 #define D_LCK (1 << 4)
36 #define G_SMRANE (1 << 3)
37 #define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
41 /* While we read PMBASE dynamically in case it changed, let's
42 * initialize it with a sane value
44 u16 pmbase = DEFAULT_PMBASE;
45 u8 smm_initialized = 0;
47 /* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located
50 global_nvs_t *gnvs = (global_nvs_t *)0x0;
51 void *tcg = (void *)0x0;
52 void *smi1 = (void *)0x0;
55 * @brief read and clear PM1_STS
56 * @return PM1_STS register
58 static u16 reset_pm1_status(void)
62 reg16 = inw(pmbase + PM1_STS);
63 /* set status bits are cleared by writing 1 to them */
64 outw(reg16, pmbase + PM1_STS);
69 static void dump_pm1_status(u16 pm1_sts)
71 printk(BIOS_SPEW, "PM1_STS: ");
72 if (pm1_sts & (1 << 15)) printk(BIOS_SPEW, "WAK ");
73 if (pm1_sts & (1 << 14)) printk(BIOS_SPEW, "PCIEXPWAK ");
74 if (pm1_sts & (1 << 11)) printk(BIOS_SPEW, "PRBTNOR ");
75 if (pm1_sts & (1 << 10)) printk(BIOS_SPEW, "RTC ");
76 if (pm1_sts & (1 << 8)) printk(BIOS_SPEW, "PWRBTN ");
77 if (pm1_sts & (1 << 5)) printk(BIOS_SPEW, "GBL ");
78 if (pm1_sts & (1 << 4)) printk(BIOS_SPEW, "BM ");
79 if (pm1_sts & (1 << 0)) printk(BIOS_SPEW, "TMROF ");
80 printk(BIOS_SPEW, "\n");
81 int reg16 = inw(pmbase + PM1_EN);
82 printk(BIOS_SPEW, "PM1_EN: %x\n", reg16);
86 * @brief read and clear SMI_STS
87 * @return SMI_STS register
89 static u32 reset_smi_status(void)
93 reg32 = inl(pmbase + SMI_STS);
94 /* set status bits are cleared by writing 1 to them */
95 outl(reg32, pmbase + SMI_STS);
100 static void dump_smi_status(u32 smi_sts)
102 printk(BIOS_DEBUG, "SMI_STS: ");
103 if (smi_sts & (1 << 26)) printk(BIOS_DEBUG, "SPI ");
104 if (smi_sts & (1 << 25)) printk(BIOS_DEBUG, "EL_SMI ");
105 if (smi_sts & (1 << 21)) printk(BIOS_DEBUG, "MONITOR ");
106 if (smi_sts & (1 << 20)) printk(BIOS_DEBUG, "PCI_EXP_SMI ");
107 if (smi_sts & (1 << 18)) printk(BIOS_DEBUG, "INTEL_USB2 ");
108 if (smi_sts & (1 << 17)) printk(BIOS_DEBUG, "LEGACY_USB2 ");
109 if (smi_sts & (1 << 16)) printk(BIOS_DEBUG, "SMBUS_SMI ");
110 if (smi_sts & (1 << 15)) printk(BIOS_DEBUG, "SERIRQ_SMI ");
111 if (smi_sts & (1 << 14)) printk(BIOS_DEBUG, "PERIODIC ");
112 if (smi_sts & (1 << 13)) printk(BIOS_DEBUG, "TCO ");
113 if (smi_sts & (1 << 12)) printk(BIOS_DEBUG, "DEVMON ");
114 if (smi_sts & (1 << 11)) printk(BIOS_DEBUG, "MCSMI ");
115 if (smi_sts & (1 << 10)) printk(BIOS_DEBUG, "GPI ");
116 if (smi_sts & (1 << 9)) printk(BIOS_DEBUG, "GPE0 ");
117 if (smi_sts & (1 << 8)) printk(BIOS_DEBUG, "PM1 ");
118 if (smi_sts & (1 << 6)) printk(BIOS_DEBUG, "SWSMI_TMR ");
119 if (smi_sts & (1 << 5)) printk(BIOS_DEBUG, "APM ");
120 if (smi_sts & (1 << 4)) printk(BIOS_DEBUG, "SLP_SMI ");
121 if (smi_sts & (1 << 3)) printk(BIOS_DEBUG, "LEGACY_USB ");
122 if (smi_sts & (1 << 2)) printk(BIOS_DEBUG, "BIOS ");
123 printk(BIOS_DEBUG, "\n");
128 * @brief read and clear GPE0_STS
129 * @return GPE0_STS register
131 static u32 reset_gpe0_status(void)
135 reg32 = inl(pmbase + GPE0_STS);
136 /* set status bits are cleared by writing 1 to them */
137 outl(reg32, pmbase + GPE0_STS);
142 static void dump_gpe0_status(u32 gpe0_sts)
145 printk(BIOS_DEBUG, "GPE0_STS: ");
146 for (i=31; i<= 16; i--) {
147 if (gpe0_sts & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", (i-16));
149 if (gpe0_sts & (1 << 14)) printk(BIOS_DEBUG, "USB4 ");
150 if (gpe0_sts & (1 << 13)) printk(BIOS_DEBUG, "PME_B0 ");
151 if (gpe0_sts & (1 << 12)) printk(BIOS_DEBUG, "USB3 ");
152 if (gpe0_sts & (1 << 11)) printk(BIOS_DEBUG, "PME ");
153 if (gpe0_sts & (1 << 10)) printk(BIOS_DEBUG, "EL_SCI/BATLOW ");
154 if (gpe0_sts & (1 << 9)) printk(BIOS_DEBUG, "PCI_EXP ");
155 if (gpe0_sts & (1 << 8)) printk(BIOS_DEBUG, "RI ");
156 if (gpe0_sts & (1 << 7)) printk(BIOS_DEBUG, "SMB_WAK ");
157 if (gpe0_sts & (1 << 6)) printk(BIOS_DEBUG, "TCO_SCI ");
158 if (gpe0_sts & (1 << 5)) printk(BIOS_DEBUG, "AC97 ");
159 if (gpe0_sts & (1 << 4)) printk(BIOS_DEBUG, "USB2 ");
160 if (gpe0_sts & (1 << 3)) printk(BIOS_DEBUG, "USB1 ");
161 if (gpe0_sts & (1 << 2)) printk(BIOS_DEBUG, "HOT_PLUG ");
162 if (gpe0_sts & (1 << 0)) printk(BIOS_DEBUG, "THRM ");
163 printk(BIOS_DEBUG, "\n");
168 * @brief read and clear TCOx_STS
169 * @return TCOx_STS registers
171 static u32 reset_tco_status(void)
173 u32 tcobase = pmbase + 0x60;
176 reg32 = inl(tcobase + 0x04);
177 /* set status bits are cleared by writing 1 to them */
178 outl(reg32 & ~(1<<18), tcobase + 0x04); // Don't clear BOOT_STS before SECOND_TO_STS
179 if (reg32 & (1 << 18))
180 outl(reg32 & (1<<18), tcobase + 0x04); // clear BOOT_STS
186 static void dump_tco_status(u32 tco_sts)
188 printk(BIOS_DEBUG, "TCO_STS: ");
189 if (tco_sts & (1 << 20)) printk(BIOS_DEBUG, "SMLINK_SLV ");
190 if (tco_sts & (1 << 18)) printk(BIOS_DEBUG, "BOOT ");
191 if (tco_sts & (1 << 17)) printk(BIOS_DEBUG, "SECOND_TO ");
192 if (tco_sts & (1 << 16)) printk(BIOS_DEBUG, "INTRD_DET ");
193 if (tco_sts & (1 << 12)) printk(BIOS_DEBUG, "DMISERR ");
194 if (tco_sts & (1 << 10)) printk(BIOS_DEBUG, "DMISMI ");
195 if (tco_sts & (1 << 9)) printk(BIOS_DEBUG, "DMISCI ");
196 if (tco_sts & (1 << 8)) printk(BIOS_DEBUG, "BIOSWR ");
197 if (tco_sts & (1 << 7)) printk(BIOS_DEBUG, "NEWCENTURY ");
198 if (tco_sts & (1 << 3)) printk(BIOS_DEBUG, "TIMEOUT ");
199 if (tco_sts & (1 << 2)) printk(BIOS_DEBUG, "TCO_INT ");
200 if (tco_sts & (1 << 1)) printk(BIOS_DEBUG, "SW_TCO ");
201 if (tco_sts & (1 << 0)) printk(BIOS_DEBUG, "NMI2SMI ");
202 printk(BIOS_DEBUG, "\n");
205 /* We are using PCIe accesses for now
206 * 1. the chipset can do it
207 * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind
209 #include "../../../northbridge/intel/i945/pcie_config.c"
211 int southbridge_io_trap_handler(int smif)
215 printk(BIOS_DEBUG, "OS Init\n");
217 * On success, the IO Trap Handler returns 0
218 * On failure, the IO Trap Handler returns a value != 0
221 return 1; /* IO trap handled */
229 * @brief Set the EOS bit
231 void southbridge_smi_set_eos(void)
235 reg8 = inb(pmbase + SMI_EN);
237 outb(reg8, pmbase + SMI_EN);
240 static void busmaster_disable_on_bus(int bus)
246 for (slot = 0; slot < 0x20; slot++) {
247 for (func = 0; func < 8; func++) {
249 device_t dev = PCI_DEV(bus, slot, func);
251 val = pci_read_config32(dev, PCI_VENDOR_ID);
253 if (val == 0xffffffff || val == 0x00000000 ||
254 val == 0x0000ffff || val == 0xffff0000)
257 /* Disable Bus Mastering for this one device */
258 reg32 = pci_read_config32(dev, PCI_COMMAND);
259 reg32 &= ~PCI_COMMAND_MASTER;
260 pci_write_config32(dev, PCI_COMMAND, reg32);
262 /* If this is a bridge, then follow it. */
263 hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
265 if (hdr == PCI_HEADER_TYPE_BRIDGE ||
266 hdr == PCI_HEADER_TYPE_CARDBUS) {
268 buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
269 busmaster_disable_on_bus((buses >> 8) & 0xff);
276 static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *state_save)
281 /* FIXME: the power state on boot should be read from
282 * CMOS or even better from GNVS. Right now it's hard
283 * coded at compile time.
285 u8 s5pwr = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
287 /* First, disable further SMIs */
288 reg8 = inb(pmbase + SMI_EN);
290 outb(reg8, pmbase + SMI_EN);
292 /* Figure out SLP_TYP */
293 reg32 = inl(pmbase + PM1_CNT);
294 printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32);
295 slp_typ = (reg32 >> 10) & 7;
297 /* Next, do the deed.
301 case 0: printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n"); break;
302 case 1: printk(BIOS_DEBUG, "SMI#: Entering S1 (Assert STPCLK#)\n"); break;
304 printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n");
305 /* Invalidate the cache before going to S3 */
308 case 6: printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n"); break;
310 printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n");
312 outl(0, pmbase + GPE0_EN);
314 /* Should we keep the power state after a power loss?
315 * In case the setting is "ON" or "OFF" we don't have
316 * to do anything. But if it's "KEEP" we have to switch
317 * to "OFF" before entering S5.
319 if (s5pwr == MAINBOARD_POWER_KEEP) {
320 reg8 = pcie_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
322 pcie_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
325 /* also iterates over all bridges on bus 0 */
326 busmaster_disable_on_bus(0);
328 default: printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n"); break;
331 /* Unlock the SMI semaphore. We're currently in SMM, and the semaphore
332 * will never be unlocked because the next outl will switch off the CPU.
333 * This might open a small race between the smi_release_lock() and the outl()
334 * for other SMI handlers. Not sure if this could cause trouble. */
338 /* Write back to the SLP register to cause the originally intended
339 * event again. We need to set BIT13 (SLP_EN) though to make the
342 outl(reg32 | SLP_EN, pmbase + PM1_CNT);
344 /* In most sleep states, the code flow of this function ends at
345 * the line above. However, if we entered sleep state S1 and wake
346 * up again, we will continue to execute code in this function.
348 reg32 = inl(pmbase + PM1_CNT);
349 if (reg32 & SCI_EN) {
350 /* The OS is not an ACPI OS, so we set the state to S0 */
351 reg32 &= ~(SLP_EN | SLP_TYP);
352 outl(reg32, pmbase + PM1_CNT);
356 static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state_save)
361 /* Emulate B2 register as the FADT / Linux expects it */
364 if (mainboard_apm_cnt && mainboard_apm_cnt(reg8))
368 case APM_CNT_CST_CONTROL:
369 /* Calling this function seems to cause
370 * some kind of race condition in Linux
371 * and causes a kernel oops
373 printk(BIOS_DEBUG, "C-state control\n");
375 case APM_CNT_PST_CONTROL:
376 /* Calling this function seems to cause
377 * some kind of race condition in Linux
378 * and causes a kernel oops
380 printk(BIOS_DEBUG, "P-state control\n");
382 case APM_CNT_ACPI_DISABLE:
383 pmctrl = inl(pmbase + PM1_CNT);
385 outl(pmctrl, pmbase + PM1_CNT);
386 printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n");
388 case APM_CNT_ACPI_ENABLE:
389 pmctrl = inl(pmbase + PM1_CNT);
391 outl(pmctrl, pmbase + PM1_CNT);
392 printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n");
394 case APM_CNT_GNVS_UPDATE:
395 if (smm_initialized) {
396 printk(BIOS_DEBUG, "SMI#: SMM structures already initialized!\n");
399 gnvs = *(global_nvs_t **)0x500;
400 tcg = *(void **)0x504;
401 smi1 = *(void **)0x508;
403 printk(BIOS_DEBUG, "SMI#: Setting up structures to %p, %p, %p\n", gnvs, tcg, smi1);
406 printk(BIOS_DEBUG, "SMI#: Unknown function APM_CNT=%02x\n", reg8);
410 static void southbridge_smi_pm1(unsigned int node, smm_state_save_area_t *state_save)
414 pm1_sts = reset_pm1_status();
415 dump_pm1_status(pm1_sts);
417 /* While OSPM is not active, poweroff immediately
418 * on a power button event.
420 if (pm1_sts & PWRBTN_STS) {
421 // power button pressed
423 reg32 = (7 << 10) | (1 << 13);
424 outl(reg32, pmbase + PM1_CNT);
428 static void southbridge_smi_gpe0(unsigned int node, smm_state_save_area_t *state_save)
432 gpe0_sts = reset_gpe0_status();
433 dump_gpe0_status(gpe0_sts);
436 static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_save)
439 reg16 = inw(pmbase + ALT_GP_SMI_STS);
440 outl(reg16, pmbase + ALT_GP_SMI_STS);
442 reg16 &= inw(pmbase + ALT_GP_SMI_EN);
444 if (mainboard_smi_gpi) {
445 mainboard_smi_gpi(reg16);
448 printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16);
452 static void southbridge_smi_mc(unsigned int node, smm_state_save_area_t *state_save)
456 reg32 = inl(pmbase + SMI_EN);
458 /* Are periodic SMIs enabled? */
459 if ((reg32 & MCSMI_EN) == 0)
462 printk(BIOS_DEBUG, "Microcontroller SMI.\n");
467 static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_save)
471 tco_sts = reset_tco_status();
477 if (tco_sts & (1 << 8)) { // BIOSWR
480 bios_cntl = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc);
483 /* BWE is RW, so the SMI was caused by a
484 * write to BWE, not by a write to the BIOS
487 /* This is the place where we notice someone
488 * is trying to tinker with the BIOS. We are
489 * trying to be nice and just ignore it. A more
490 * resolute answer would be to power down the
493 printk(BIOS_DEBUG, "Switching back to RO\n");
494 pcie_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1));
495 } /* No else for now? */
496 } else if (tco_sts & (1 << 3)) { /* TIMEOUT */
497 /* Handle TCO timeout */
498 printk(BIOS_DEBUG, "TCO Timeout.\n");
499 } else if (!tco_sts) {
500 dump_tco_status(tco_sts);
504 static void southbridge_smi_periodic(unsigned int node, smm_state_save_area_t *state_save)
508 reg32 = inl(pmbase + SMI_EN);
510 /* Are periodic SMIs enabled? */
511 if ((reg32 & PERIODIC_EN) == 0)
514 printk(BIOS_DEBUG, "Periodic SMI.\n");
517 static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *state_save)
519 #define IOTRAP(x) (trap_sts & (1 << x))
520 u32 trap_sts, trap_cycle;
524 trap_sts = RCBA32(0x1e00); // TRSR - Trap Status Register
525 RCBA32(0x1e00) = trap_sts; // Clear trap(s) in TRSR
527 trap_cycle = RCBA32(0x1e10);
528 for (i=16; i<20; i++) {
529 if (trap_cycle & (1 << i))
530 mask |= (0xff << ((i - 16) << 2));
534 /* IOTRAP(3) SMI function call */
536 if (gnvs && gnvs->smif)
537 io_trap_handler(gnvs->smif); // call function smif
541 /* IOTRAP(2) currently unused
542 * IOTRAP(1) currently unused */
546 if (!(trap_cycle & (1 << 24))) { // It's a write
547 printk(BIOS_DEBUG, "SMI1 command\n");
548 data = RCBA32(0x1e18);
551 // southbridge_smi_command(data);
554 // Fall through to debug
557 printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc);
558 for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAPĀ = %d\n", i);
559 printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf);
560 printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask);
561 printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write");
563 if (!(trap_cycle & (1 << 24))) {
565 data = RCBA32(0x1e18);
566 printk(BIOS_DEBUG, " iotrap written data = 0x%08x\n", data);
571 typedef void (*smi_handler_t)(unsigned int node,
572 smm_state_save_area_t *state_save);
574 smi_handler_t southbridge_smi[32] = {
575 NULL, // [0] reserved
576 NULL, // [1] reserved
577 NULL, // [2] BIOS_STS
578 NULL, // [3] LEGACY_USB_STS
579 southbridge_smi_sleep, // [4] SLP_SMI_STS
580 southbridge_smi_apmc, // [5] APM_STS
581 NULL, // [6] SWSMI_TMR_STS
582 NULL, // [7] reserved
583 southbridge_smi_pm1, // [8] PM1_STS
584 southbridge_smi_gpe0, // [9] GPE0_STS
585 southbridge_smi_gpi, // [10] GPI_STS
586 southbridge_smi_mc, // [11] MCSMI_STS
587 NULL, // [12] DEVMON_STS
588 southbridge_smi_tco, // [13] TCO_STS
589 southbridge_smi_periodic, // [14] PERIODIC_STS
590 NULL, // [15] SERIRQ_SMI_STS
591 NULL, // [16] SMBUS_SMI_STS
592 NULL, // [17] LEGACY_USB2_STS
593 NULL, // [18] INTEL_USB2_STS
594 NULL, // [19] reserved
595 NULL, // [20] PCI_EXP_SMI_STS
596 southbridge_smi_monitor, // [21] MONITOR_STS
597 NULL, // [22] reserved
598 NULL, // [23] reserved
599 NULL, // [24] reserved
600 NULL, // [25] EL_SMI_STS
601 NULL, // [26] SPI_STS
602 NULL, // [27] reserved
603 NULL, // [28] reserved
604 NULL, // [29] reserved
605 NULL, // [30] reserved
606 NULL // [31] reserved
610 * @brief Interrupt handler for SMI#
612 * @param smm_revision revision of the smm state save map
615 void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save)
620 /* Update global variable pmbase */
621 pmbase = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
623 /* We need to clear the SMI status registers, or we won't see what's
624 * happening in the following calls.
626 smi_sts = reset_smi_status();
628 /* Filter all non-enabled SMI events */
629 // FIXME Double check, this clears MONITOR
630 // smi_sts &= inl(pmbase + SMI_EN);
632 /* Call SMI sub handler for each of the status bits */
633 for (i = 0; i < 31; i++) {
634 if (smi_sts & (1 << i)) {
635 if (southbridge_smi[i])
636 southbridge_smi[i](node, state_save);
638 printk(BIOS_DEBUG, "SMI_STS[%d] occured, but no "
639 "handler available.\n", i);
646 dump_smi_status(smi_sts);