src/southbridge/intel/i82801gx/sata.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008-2009 coresystems GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; version 2 of
   9  * the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  19  */
  20
  21 #include <console/console.h>
  22 #include <device/device.h>
  23 #include <device/pci.h>
  24 #include <device/pci_ids.h>
  25 #include "i82801gx.h"
  26
  27 typedef struct southbridge_intel_i82801gx_config config_t;
  28
  29 static void sata_init(struct device *dev)
  30 {
  31         u32 reg32;
  32         u16 reg16;
  33         u32 *ahci_bar;
  34
  35         /* Get the chip configuration */
  36         config_t *config = dev->chip_info;
  37
  38         printk(BIOS_DEBUG, "i82801gx_sata: initializing...\n");
  39
  40         if (config == NULL) {
  41                 printk(BIOS_ERR, "i82801gx_sata: error: device not in devicetree.cb!\n");
  42                 return;
  43         }
  44
  45         /* SATA configuration */
  46
  47         /* Enable BARs */
  48         pci_write_config16(dev, PCI_COMMAND, 0x0007);
  49
  50         if (config->ide_legacy_combined) {
  51                 printk(BIOS_DEBUG, "SATA controller in combined mode.\n");
  52                 /* No AHCI: clear AHCI base */
  53                 pci_write_config32(dev, 0x24, 0x00000000);
  54                 /* And without AHCI BAR no memory decoding */
  55                 reg16 = pci_read_config16(dev, PCI_COMMAND);
  56                 reg16 &= ~PCI_COMMAND_MEMORY;
  57                 pci_write_config16(dev, PCI_COMMAND, reg16);
  58
  59                 pci_write_config8(dev, 0x09, 0x80);
  60
  61                 /* Set timings */
  62                 pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
  63                                 IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
  64                 pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
  65                                 IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
  66                                 IDE_PPE0 | IDE_IE0 | IDE_TIME0);
  67
  68                 /* Sync DMA */
  69                 pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0);
  70                 pci_write_config16(dev, IDE_SDMA_TIM, 0x0200);
  71
  72                 /* Set IDE I/O Configuration */
  73                 reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
  74                 pci_write_config32(dev, IDE_CONFIG, reg32);
  75
  76                 /* Combine IDE - SATA configuration */
  77                 pci_write_config8(dev, 0x90, 0x02);
  78
  79                 /* Port 0 & 1 enable */
  80                 pci_write_config8(dev, 0x92, 0x0f);
  81
  82                 /* SATA Initialization register */
  83                 pci_write_config32(dev, 0x94, 0x5a000180);
  84         } else if(config->sata_ahci) {
  85                 printk(BIOS_DEBUG, "SATA controller in AHCI mode.\n");
  86                 /* Allow both Legacy and Native mode */
  87                 pci_write_config8(dev, 0x09, 0x8f);
  88
  89                 /* Set Interrupt Line */
  90                 /* Interrupt Pin is set by D31IP.PIP */
  91                 pci_write_config8(dev, INTR_LN, 0x0a);
  92
  93                 /* Set timings */
  94                 pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
  95                                 IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
  96                                 IDE_PPE0 | IDE_IE0 | IDE_TIME0);
  97                 pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
  98                                 IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
  99
 100                 /* Sync DMA */
 101                 pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0);
 102                 pci_write_config16(dev, IDE_SDMA_TIM, 0x0001);
 103
 104                 /* Set IDE I/O Configuration */
 105                 reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
 106                 pci_write_config32(dev, IDE_CONFIG, reg32);
 107
 108                 /* Set Sata Controller Mode. */
 109                 pci_write_config8(dev, 0x90, 0x40); // 40=AHCI
 110
 111                 /* In ACHI mode, bit[3:0] must always be set
 112                  * (Port status is controlled through AHCI BAR)
 113                  */
 114                 pci_write_config8(dev, 0x92, 0x0f);
 115
 116                 ahci_bar = (u32 *)(pci_read_config32(dev, 0x27) & ~0x3ff);
 117                 ahci_bar[3] = config->sata_ports_implemented;
 118
 119                 /* SATA Initialization register */
 120                 pci_write_config32(dev, 0x94, 0x1a000180);
 121         } else {
 122                 printk(BIOS_DEBUG, "SATA controller in plain mode.\n");
 123                 /* Set Sata Controller Mode. No Mapping(?) */
 124                 pci_write_config8(dev, 0x90, 0x00);
 125
 126                 /* No AHCI: clear AHCI base */
 127                 pci_write_config32(dev, 0x24, 0x00000000);
 128
 129                 /* And without AHCI BAR no memory decoding */
 130                 reg16 = pci_read_config16(dev, PCI_COMMAND);
 131                 reg16 &= ~PCI_COMMAND_MEMORY;
 132                 pci_write_config16(dev, PCI_COMMAND, reg16);
 133
 134                 /* Native mode capable on both primary and secondary (0xa)
 135                  * or'ed with enabled (0x50) = 0xf
 136                  */
 137                 pci_write_config8(dev, 0x09, 0x8f);
 138
 139                 /* Set Interrupt Line */
 140                 /* Interrupt Pin is set by D31IP.PIP */
 141                 pci_write_config8(dev, INTR_LN, 0xff);
 142
 143                 /* Set timings */
 144                 pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
 145                                 IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
 146                                 IDE_PPE0 | IDE_IE0 | IDE_TIME0);
 147                 pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
 148                                 IDE_SITRE | IDE_ISP_3_CLOCKS |
 149                                 IDE_RCT_1_CLOCKS | IDE_IE0 | IDE_TIME0);
 150
 151                 /* Sync DMA */
 152                 pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0 | IDE_PSDE0);
 153                 pci_write_config16(dev, IDE_SDMA_TIM, 0x0201);
 154
 155                 /* Set IDE I/O Configuration */
 156                 reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
 157                 pci_write_config32(dev, IDE_CONFIG, reg32);
 158
 159                 /* Port 0 & 1 enable XXX */
 160                 pci_write_config8(dev, 0x92, 0x15);
 161
 162                 /* SATA Initialization register */
 163                 pci_write_config32(dev, 0x94, 0x1a000180);
 164         }
 165
 166         /* All configurations need this SATA initialization sequence */
 167         pci_write_config8(dev, 0xa0, 0x40);
 168         pci_write_config8(dev, 0xa6, 0x22);
 169         pci_write_config8(dev, 0xa0, 0x78);
 170         pci_write_config8(dev, 0xa6, 0x22);
 171         pci_write_config8(dev, 0xa0, 0x88);
 172         reg32 = pci_read_config32(dev, 0xa4);
 173         reg32 &= 0xc0c0c0c0;
 174         reg32 |= 0x1b1b1212;
 175         pci_write_config32(dev, 0xa4, reg32);
 176         pci_write_config8(dev, 0xa0, 0x8c);
 177         reg32 = pci_read_config32(dev, 0xa4);
 178         reg32 &= 0xc0c0ff00;
 179         reg32 |= 0x121200aa;
 180         pci_write_config32(dev, 0xa4, reg32);
 181         pci_write_config8(dev, 0xa0, 0x00);
 182
 183         pci_write_config8(dev, PCI_INTERRUPT_LINE, 0);
 184
 185         /* Sata Initialization Register */
 186         reg32 = pci_read_config32(dev, 0x94);
 187         reg32 |= (1 << 30); // due to some bug
 188         pci_write_config32(dev, 0x94, reg32);
 189 }
 190
 191 static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 192 {
 193         if (!vendor || !device) {
 194                 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
 195                                 pci_read_config32(dev, PCI_VENDOR_ID));
 196         } else {
 197                 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
 198                                 ((device & 0xffff) << 16) | (vendor & 0xffff));
 199         }
 200 }
 201
 202 static struct pci_operations sata_pci_ops = {
 203         .set_subsystem    = sata_set_subsystem,
 204 };
 205
 206 static struct device_operations sata_ops = {
 207         .read_resources         = pci_dev_read_resources,
 208         .set_resources          = pci_dev_set_resources,
 209         .enable_resources       = pci_dev_enable_resources,
 210         .init                   = sata_init,
 211         .scan_bus               = 0,
 212         .enable                 = i82801gx_enable,
 213         .ops_pci                = &sata_pci_ops,
 214 };
 215
 216 /* Desktop Non-AHCI and Non-RAID Mode */
 217 /* 82801GB/GR/GDH (ICH7/ICH7R/ICH7DH) */
 218 static const struct pci_driver i82801gx_sata_normal_driver __pci_driver = {
 219         .ops    = &sata_ops,
 220         .vendor = PCI_VENDOR_ID_INTEL,
 221         .device = 0x27c0,
 222 };
 223
 224 /* Mobile Non-AHCI and Non-RAID Mode */
 225 /* 82801GBM/GHM (ICH7-M/ICH7-M DH) */
 226 static const struct pci_driver i82801gx_sata_mobile_normal_driver __pci_driver = {
 227         .ops    = &sata_ops,
 228         .vendor = PCI_VENDOR_ID_INTEL,
 229         .device = 0x27c4,
 230 };
 231
 232
 233 /* NOTE: Any of the below are not properly supported yet. */
 234
 235 /* Desktop AHCI Mode */
 236 /* 82801GB/GR/GDH (ICH7/ICH7R/ICH7DH) */
 237 static const struct pci_driver i82801gx_sata_ahci_driver __pci_driver = {
 238         .ops    = &sata_ops,
 239         .vendor = PCI_VENDOR_ID_INTEL,
 240         .device = 0x27c1,
 241 };
 242
 243 /* Desktop RAID mode */
 244 /* 82801GB/GR/GDH (ICH7/ICH7R/ICH7DH) */
 245 static const struct pci_driver i82801gx_sata_raid_driver __pci_driver = {
 246         .ops    = &sata_ops,
 247         .vendor = PCI_VENDOR_ID_INTEL,
 248         .device = 0x27c3,
 249 };
 250
 251 /* Mobile AHCI Mode */
 252 /* 82801GBM/GHM (ICH7-M/ICH7-M DH) */
 253 static const struct pci_driver i82801gx_sata_mobile_ahci_driver __pci_driver = {
 254         .ops    = &sata_ops,
 255         .vendor = PCI_VENDOR_ID_INTEL,
 256         .device = 0x27c5,
 257 };
 258
 259 /* ICH7M DH Raid Mode */
 260 /* 82801GHM (ICH7-M DH) */
 261 static const struct pci_driver i82801gx_sata_ich7dh_raid_driver __pci_driver = {
 262         .ops    = &sata_ops,
 263         .vendor = PCI_VENDOR_ID_INTEL,
 264         .device = 0x27c6,
 265 };