2 * This file is part of the coreboot project.
4 * Copyright (C) 2008-2009 coresystems GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <console/console.h>
22 #include <device/device.h>
23 #include <device/pci.h>
24 #include <device/pci_ids.h>
26 #if CONFIG_USBDEBUG_DIRECT
27 #include <usbdebug_direct.h>
31 static void usb_ehci_init(struct device *dev)
38 printk(BIOS_DEBUG, "EHCI: Setting up controller.. ");
39 reg32 = pci_read_config32(dev, PCI_COMMAND);
40 reg32 |= PCI_COMMAND_MASTER;
41 reg32 |= PCI_COMMAND_SERR;
42 pci_write_config32(dev, PCI_COMMAND, reg32);
44 reg32 = pci_read_config32(dev, 0xdc);
45 reg32 |= (1 << 31) | (1 << 27);
46 pci_write_config32(dev, 0xdc, reg32);
48 reg32 = pci_read_config32(dev, 0xfc);
50 reg32 |= (2 << 2) | (1 << 29) | (1 << 17);
51 pci_write_config32(dev, 0xfc, reg32);
53 /* Clear any pending port changes */
54 res = find_resource(dev, 0x10);
56 reg32 = read32(base + 0x24) | (1 << 2);
57 write32(base + 0x24, reg32);
60 reg8 = pci_read_config8(dev, 0x84);
62 pci_write_config8(dev, 0x84, reg8);
64 printk(BIOS_DEBUG, "done.\n");
67 static void usb_ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
71 access_cntl = pci_read_config8(dev, 0x80);
73 /* Enable writes to protected registers. */
74 pci_write_config8(dev, 0x80, access_cntl | 1);
76 if (!vendor || !device) {
77 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
78 pci_read_config32(dev, PCI_VENDOR_ID));
80 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
81 ((device & 0xffff) << 16) | (vendor & 0xffff));
84 /* Restore protection. */
85 pci_write_config8(dev, 0x80, access_cntl);
88 static void usb_ehci_set_resources(struct device *dev)
90 #if CONFIG_USBDEBUG_DIRECT
95 usb_debug = get_ehci_debug();
98 pci_dev_set_resources(dev);
100 #if CONFIG_USBDEBUG_DIRECT
101 res = find_resource(dev, 0x10);
102 set_ehci_debug(usb_debug);
106 report_resource_stored(dev, res, "");
112 static struct pci_operations lops_pci = {
113 .set_subsystem = &usb_ehci_set_subsystem,
116 static struct device_operations usb_ehci_ops = {
117 .read_resources = pci_dev_read_resources,
118 .set_resources = usb_ehci_set_resources,
119 .enable_resources = pci_dev_enable_resources,
120 .init = usb_ehci_init,
122 .enable = i82801gx_enable,
123 .ops_pci = &lops_pci,
126 /* 82801GB/GR/GDH/GBM/GHM/GU (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH/ICH7-U) */
127 static const struct pci_driver i82801gx_usb_ehci __pci_driver = {
128 .ops = &usb_ehci_ops,
129 .vendor = PCI_VENDOR_ID_INTEL,