src/southbridge/intel/i82801gx/i82801gx_usb.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008-2009 coresystems GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; version 2 of
   9  * the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  19  */
  20
  21 #include <console/console.h>
  22 #include <device/device.h>
  23 #include <device/pci.h>
  24 #include <device/pci_ids.h>
  25 #include "i82801gx.h"
  26
  27 static void usb_init(struct device *dev)
  28 {
  29         u32 reg32;
  30         u8 reg8;
  31
  32         /* USB Specification says the device must be Bus Master */
  33         printk_debug("UHCI: Setting up controller.. ");
  34
  35         reg32 = pci_read_config32(dev, PCI_COMMAND);
  36         pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);
  37
  38         // Erratum
  39         pci_write_config8(dev, 0xca, 0x00);
  40
  41         // Yes. Another Erratum
  42         reg8 = pci_read_config8(dev, 0xca);
  43         reg8 |= (1 << 0);
  44         pci_write_config8(dev, 0xca, reg8);
  45
  46         printk_debug("done.\n");
  47 }
  48
  49 static void usb_set_subsystem(device_t dev, unsigned vendor, unsigned device)
  50 {
  51         if (!vendor || !device) {
  52                 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
  53                                 pci_read_config32(dev, PCI_VENDOR_ID));
  54         } else {
  55                 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
  56                                 ((device & 0xffff) << 16) | (vendor & 0xffff));
  57         }
  58 }
  59
  60 static struct pci_operations usb_pci_ops = {
  61         .set_subsystem    = usb_set_subsystem,
  62 };
  63
  64 static struct device_operations usb_ops = {
  65         .read_resources         = pci_dev_read_resources,
  66         .set_resources          = pci_dev_set_resources,
  67         .enable_resources       = pci_dev_enable_resources,
  68         .init                   = usb_init,
  69         .scan_bus               = 0,
  70         .enable                 = i82801gx_enable,
  71         .ops_pci                = &usb_pci_ops,
  72 };
  73
  74 /* 82801GB/GR/GDH/GBM/GHM/GU (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH/ICH7-U) */
  75 static const struct pci_driver i82801gb_usb1 __pci_driver = {
  76         .ops    = &usb_ops,
  77         .vendor = PCI_VENDOR_ID_INTEL,
  78         .device = 0x27c8,
  79 };
  80
  81 /* 82801GB/GR/GDH/GBM/GHM/GU (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH/ICH7-U) */
  82 static const struct pci_driver i82801gb_usb2 __pci_driver = {
  83         .ops    = &usb_ops,
  84         .vendor = PCI_VENDOR_ID_INTEL,
  85         .device = 0x27c9,
  86 };
  87
  88 /* 82801GB/GR/GDH/GBM/GHM/GU (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH/ICH7-U) */
  89 static const struct pci_driver i82801gb_usb3 __pci_driver = {
  90         .ops    = &usb_ops,
  91         .vendor = PCI_VENDOR_ID_INTEL,
  92         .device = 0x27ca,
  93 };
  94
  95 /* 82801GB/GR/GDH/GBM/GHM/GU (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH/ICH7-U) */
  96 static const struct pci_driver i82801gb_usb4 __pci_driver = {
  97         .ops    = &usb_ops,
  98         .vendor = PCI_VENDOR_ID_INTEL,
  99         .device = 0x27cb,
 100 };