src/southbridge/intel/i82801gx/i82801gx_smbus.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008-2009 coresystems GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; version 2 of
   9  * the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  19  */
  20
  21 #include <console/console.h>
  22 #include <device/device.h>
  23 #include <device/path.h>
  24 #include <device/smbus.h>
  25 #include <device/pci.h>
  26 #include <device/pci_ids.h>
  27 #include <device/pci_ops.h>
  28 #include <arch/io.h>
  29 #include "i82801gx.h"
  30 #include "i82801gx_smbus.h"
  31
  32 #define SMB_BASE 0x20
  33 static void smbus_init(struct device *dev)
  34 {
  35         u32 smb_base;
  36
  37         smb_base = pci_read_config32(dev, SMB_BASE);
  38         printk(BIOS_DEBUG, "Initializing SMBus device:\n");
  39         printk(BIOS_DEBUG, "  Old SMBUS Base Address: 0x%04x\n", smb_base);
  40         pci_write_config32(dev, SMB_BASE, 0x00000401);
  41         smb_base = pci_read_config32(dev, SMB_BASE);
  42         printk(BIOS_DEBUG, "  New SMBUS Base Address: 0x%04x\n", smb_base);
  43 }
  44
  45 static int lsmbus_read_byte(device_t dev, u8 address)
  46 {
  47         u16 device;
  48         struct resource *res;
  49         struct bus *pbus;
  50
  51         device = dev->path.i2c.device;
  52         pbus = get_pbus_smbus(dev);
  53         res = find_resource(pbus->dev, 0x20);
  54
  55         return do_smbus_read_byte(res->base, device, address);
  56 }
  57
  58 static struct smbus_bus_operations lops_smbus_bus = {
  59         .read_byte      = lsmbus_read_byte,
  60 };
  61
  62 static void smbus_set_subsystem(device_t dev, unsigned vendor, unsigned device)
  63 {
  64         if (!vendor || !device) {
  65                 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
  66                                 pci_read_config32(dev, PCI_VENDOR_ID));
  67         } else {
  68                 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
  69                                 ((device & 0xffff) << 16) | (vendor & 0xffff));
  70         }
  71 }
  72
  73 static struct pci_operations smbus_pci_ops = {
  74         .set_subsystem    = smbus_set_subsystem,
  75 };
  76
  77 static struct device_operations smbus_ops = {
  78         .read_resources         = pci_dev_read_resources,
  79         .set_resources          = pci_dev_set_resources,
  80         .enable_resources       = pci_dev_enable_resources,
  81         .init                   = smbus_init,
  82         .scan_bus               = scan_static_bus,
  83         .enable                 = i82801gx_enable,
  84         .ops_smbus_bus          = &lops_smbus_bus,
  85         .ops_pci                = &smbus_pci_ops,
  86 };
  87
  88 /* 82801GB/GR/GDH/GBM/GHM/GU (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH/ICH7-U) */
  89 static const struct pci_driver i82801gx_smbus __pci_driver = {
  90         .ops    = &smbus_ops,
  91         .vendor = PCI_VENDOR_ID_INTEL,
  92         .device = 0x27da,
  93 };