src/southbridge/intel/i82801gx/i82801gx_lpc.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008 coresystems GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  19  */
  20
  21 #include <console/console.h>
  22 #include <device/device.h>
  23 #include <device/pci.h>
  24 #include <device/pci_ids.h>
  25 #include <pc80/mc146818rtc.h>
  26 #include <pc80/isa-dma.h>
  27 #include <arch/io.h>
  28 #include "i82801gx.h"
  29
  30 #include "../../../northbridge/intel/i945/ich7.h"
  31
  32 #define MAINBOARD_POWER_OFF 0
  33 #define MAINBOARD_POWER_ON  1
  34
  35 #ifndef MAINBOARD_POWER_ON_AFTER_FAIL
  36 #define MAINBOARD_POWER_ON_AFTER_FAIL MAINBOARD_POWER_ON
  37 #endif
  38
  39 #define NMI_OFF 0
  40
  41 /* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
  42  * 0x00 - 0000 = Reserved
  43  * 0x01 - 0001 = Reserved
  44  * 0x02 - 0010 = Reserved
  45  * 0x03 - 0011 = IRQ3
  46  * 0x04 - 0100 = IRQ4
  47  * 0x05 - 0101 = IRQ5
  48  * 0x06 - 0110 = IRQ6
  49  * 0x07 - 0111 = IRQ7
  50  * 0x08 - 1000 = Reserved
  51  * 0x09 - 1001 = IRQ9
  52  * 0x0A - 1010 = IRQ10
  53  * 0x0B - 1011 = IRQ11
  54  * 0x0C - 1100 = IRQ12
  55  * 0x0D - 1101 = Reserved
  56  * 0x0E - 1110 = IRQ14
  57  * 0x0F - 1111 = IRQ15
  58  * PIRQ[n]_ROUT[7] - PIRQ Routing Control
  59  * 0x80 - The PIRQ is not routed.
  60  */
  61
  62 #define PIRQA 0x03
  63 #define PIRQB 0x05
  64 #define PIRQC 0x06
  65 #define PIRQD 0x07
  66 #define PIRQE 0x09
  67 #define PIRQF 0x0A
  68 #define PIRQG 0x0B
  69 #define PIRQH 0x0C
  70
  71 static void i82801gx_enable_apic(struct device *dev)
  72 {
  73         int i;
  74         u32 reg32;
  75         volatile u32 *ioapic_index = (volatile u32 *)0xfec00000;
  76         volatile u32 *ioapic_data = (volatile u32 *)0xfec00010;
  77
  78         /* Enable ACPI I/O and power management. */
  79         pci_write_config8(dev, ACPI_CNTL, 0x80);
  80
  81         *ioapic_index = 0;
  82         *ioapic_data = (1 << 25);
  83
  84         *ioapic_index = 0;
  85         reg32 = *ioapic_data;
  86         printk_debug("Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f);
  87         if (reg32 != (1 << 25))
  88                 die("APIC Error\n");
  89
  90         printk_spew("Dumping IOAPIC registers\n");
  91         for (i=0; i<3; i++) {
  92                 *ioapic_index = i;
  93                 printk_spew("  reg 0x%04x:", i);
  94                 reg32 = *ioapic_data;
  95                 printk_spew(" 0x%08x\n", reg32);
  96         }
  97
  98         *ioapic_index = 3; /* Select Boot Configuration register. */
  99         *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */
 100 }
 101
 102 static void i82801gx_enable_serial_irqs(struct device *dev)
 103 {
 104         /* Set packet length and toggle silent mode bit for one frame. */
 105         pci_write_config8(dev, SERIRQ_CNTL,
 106                           (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));
 107 }
 108
 109 static void i82801gx_pirq_init(device_t dev)
 110 {
 111         pci_write_config8(dev, PIRQA_ROUT, 0x85);
 112         pci_write_config8(dev, PIRQB_ROUT, 0x87);
 113         pci_write_config8(dev, PIRQC_ROUT, 0x86);
 114         pci_write_config8(dev, PIRQD_ROUT, 0x87);
 115
 116         pci_write_config8(dev, PIRQE_ROUT, 0x80);
 117         pci_write_config8(dev, PIRQF_ROUT, 0x80);
 118         pci_write_config8(dev, PIRQG_ROUT, 0x80);
 119         pci_write_config8(dev, PIRQH_ROUT, 0x85);
 120 }
 121
 122 static void i82801gx_power_options(device_t dev)
 123 {
 124         u8 reg8;
 125         u16 reg16;
 126
 127         int pwr_on=MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
 128         int nmi_option;
 129
 130         /* Which state do we want to goto after g3 (power restored)?
 131          * 0 == S0 Full On
 132          * 1 == S5 Soft Off
 133          */
 134         get_option(&pwr_on, "power_on_after_fail");
 135         reg8 = pci_read_config8(dev, GEN_PMCON_3);
 136         reg8 &= 0xfe;
 137         if (pwr_on) {
 138                 reg8 &= ~1;
 139         } else {
 140                 reg8 |= 1;
 141         }
 142         reg8 |= (3 << 4);       /* avoid #S4 assertions */
 143
 144         pci_write_config8(dev, GEN_PMCON_3, reg8);
 145         printk_info("Set power %s after power failure.\n", pwr_on ? "on" : "off");
 146
 147         /* Set up NMI on errors. */
 148         reg8 = inb(0x61);
 149         reg8 &= 0x0f;           /* Higher Nibble must be 0 */
 150         reg8 &= ~(1 << 3);      /* IOCHK# NMI Enable */
 151         // reg8 &= ~(1 << 2);   /* PCI SERR# Enable */
 152         reg8 |= (1 << 2); /* PCI SERR# Disable for now */
 153         outb(reg8, 0x61);
 154
 155         reg8 = inb(0x70);
 156         nmi_option = NMI_OFF;
 157         get_option(&nmi_option, "nmi");
 158         if (nmi_option) {
 159                 printk_info ("NMI sources enabled.\n");
 160                 reg8 &= ~(1 << 7);      /* Set NMI. */
 161         } else {
 162                 printk_info ("NMI sources disabled.\n");
 163                 reg8 |= ( 1 << 7);      /* Can't mask NMI from PCI-E and NMI_NOW */
 164         }
 165         outb(reg8, 0x70);
 166
 167         // Enable CPU_SLP# and Intel Speedstep, set SMI# rate down
 168         reg16 = pci_read_config16(dev, GEN_PMCON_1);
 169         reg16 &= ~3;
 170         reg16 |= (1 << 3) | (1 << 5) | (1 << 10);
 171         pci_write_config16(dev, GEN_PMCON_1, reg16);
 172
 173         // Set GPIO13 to SCI (?)
 174         // This might be board specific
 175         pci_write_config32(dev, 0xb8, 0x08000000);
 176 }
 177
 178 void i82801gx_rtc_init(struct device *dev)
 179 {
 180         u8 reg8;
 181         u32 reg32;
 182         int rtc_failed;
 183
 184         reg8 = pci_read_config8(dev, GEN_PMCON_3);
 185         rtc_failed = reg8 & RTC_BATTERY_DEAD;
 186         if (rtc_failed) {
 187                 reg8 &= ~RTC_BATTERY_DEAD;
 188                 pci_write_config8(dev, GEN_PMCON_3, reg8);
 189         }
 190         printk_debug("rtc_failed = 0x%x\n", rtc_failed);
 191
 192         rtc_init(rtc_failed);
 193 }
 194
 195 static void enable_hpet(struct device *dev)
 196 {
 197         /* TODO */
 198 }
 199
 200 static void i82801gx_lock_smm(struct device *dev)
 201 {
 202         void smm_lock(void);
 203         u8 reg8;
 204
 205 #if ENABLE_ACPI_MODE_IN_COREBOOT
 206         printk_debug("Enabling ACPI via APMC:\n");
 207         outb(0xe1, 0xb2); // Enable ACPI mode
 208         printk_debug("done.\n");
 209 #else
 210         printk_debug("Disabling ACPI via APMC:\n");
 211         outb(0x1e, 0xb2); // Disable ACPI mode
 212         printk_debug("done.\n");
 213 #endif
 214         /* Don't allow evil boot loaders, kernels, or
 215          * userspace applications to deceive us:
 216          */
 217         smm_lock();
 218
 219 #if TEST_SMM_FLASH_LOCKDOWN
 220         /* Now try this: */
 221         printk_debug("Locking BIOS to RO... ");
 222         reg8 = pci_read_config8(dev, 0xdc);     /* BIOS_CNTL */
 223         printk_debug(" BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
 224                         (reg8&1)?"rw":"ro");
 225         reg8 &= ~(1 << 0);                      /* clear BIOSWE */
 226         pci_write_config8(dev, 0xdc, reg8);
 227         reg8 |= (1 << 1);                       /* set BLE */
 228         pci_write_config8(dev, 0xdc, reg8);
 229         printk_debug("ok.\n");
 230         reg8 = pci_read_config8(dev, 0xdc);     /* BIOS_CNTL */
 231         printk_debug(" BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
 232                         (reg8&1)?"rw":"ro");
 233
 234         printk_debug("Writing:\n");
 235         *(volatile u8 *)0xfff00000 = 0x00;
 236         printk_debug("Testing:\n");
 237         reg8 |= (1 << 0);                       /* set BIOSWE */
 238         pci_write_config8(dev, 0xdc, reg8);
 239
 240         reg8 = pci_read_config8(dev, 0xdc);     /* BIOS_CNTL */
 241         printk_debug(" BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
 242                         (reg8&1)?"rw":"ro");
 243         printk_debug("Done.\n");
 244 #endif
 245 }
 246
 247 static void lpc_init(struct device *dev)
 248 {
 249         printk_debug("i82801gx: lpc_init\n");
 250
 251         /* Set the value for PCI command register. */
 252         pci_write_config16(dev, PCI_COMMAND, 0x000f);
 253
 254         /* IO APIC initialization. */
 255         i82801gx_enable_apic(dev);
 256
 257         i82801gx_enable_serial_irqs(dev);
 258
 259         /* Setup the PIRQ. */
 260         i82801gx_pirq_init(dev);
 261
 262         /* Setup power options. */
 263         i82801gx_power_options(dev);
 264
 265         /* Set the state of the GPIO lines. */
 266         //gpio_init(dev);
 267
 268         /* Initialize the real time clock. */
 269         i82801gx_rtc_init(dev);
 270
 271         /* Initialize ISA DMA. */
 272         isa_dma_init();
 273
 274         /* Initialize the High Precision Event Timers, if present. */
 275         enable_hpet(dev);
 276
 277         setup_i8259();
 278
 279         i82801gx_lock_smm(dev);
 280 }
 281
 282 static void i82801gx_lpc_read_resources(device_t dev)
 283 {
 284         struct resource *res;
 285
 286         /* Get the normal PCI resources of this device. */
 287         pci_dev_read_resources(dev);
 288
 289         /* Add an extra subtractive resource for both memory and I/O. */
 290         res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
 291         res->flags =
 292             IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
 293
 294         res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
 295         res->flags =
 296             IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
 297 }
 298
 299 static void i82801gx_lpc_enable_resources(device_t dev)
 300 {
 301         pci_dev_enable_resources(dev);
 302         enable_childrens_resources(dev);
 303 }
 304
 305 static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
 306 {
 307         printk_debug("Setting LPC bridge subsystem ID\n");
 308         pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
 309                         pci_read_config32(dev, 0));
 310 }
 311
 312 static struct pci_operations pci_ops = {
 313         .set_subsystem = set_subsystem,
 314 };
 315
 316 static struct device_operations device_ops = {
 317         .read_resources         = i82801gx_lpc_read_resources,
 318         .set_resources          = pci_dev_set_resources,
 319         .enable_resources       = i82801gx_lpc_enable_resources,
 320         .init                   = lpc_init,
 321         .scan_bus               = scan_static_bus,
 322         .enable                 = i82801gx_enable,
 323         .ops_pci                = &pci_ops,
 324 };
 325
 326 /* 82801GB/GR/GDH (ICH7/ICH7R/ICH7DH) */
 327 static const struct pci_driver ich7_ich7r_ich7dh_lpc __pci_driver = {
 328         .ops    = &device_ops,
 329         .vendor = PCI_VENDOR_ID_INTEL,
 330         .device = 0x27b8,
 331 };
 332
 333 /* 82801GBM/GU (ICH7-M/ICH7-U) */
 334 static const struct pci_driver ich7m_ich7u_lpc __pci_driver = {
 335         .ops    = &device_ops,
 336         .vendor = PCI_VENDOR_ID_INTEL,
 337         .device = 0x27b9,
 338 };
 339
 340 /* 82801GHM (ICH7-M DH) */
 341 static const struct pci_driver ich7m_dh_lpc __pci_driver = {
 342         .ops    = &device_ops,
 343         .vendor = PCI_VENDOR_ID_INTEL,
 344         .device = 0x27bd,
 345 };