src/southbridge/intel/i82801gx/i82801gx_ide.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008-2009 coresystems GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; version 2 of
   9  * the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  19  */
  20
  21 #include <console/console.h>
  22 #include <device/device.h>
  23 #include <device/pci.h>
  24 #include <device/pci_ids.h>
  25 #include "i82801gx.h"
  26
  27 typedef struct southbridge_intel_i82801gx_config config_t;
  28
  29 static void ide_init(struct device *dev)
  30 {
  31         u16 ideTimingConfig;
  32         u32 reg32;
  33         u32 enable_primary, enable_secondary;
  34
  35         /* Get the chip configuration */
  36         config_t *config = dev->chip_info;
  37
  38         printk(BIOS_DEBUG, "i82801gx_ide: initializing... ");
  39         if (config == NULL) {
  40                 printk(BIOS_ERR, "\ni82801gx_ide: Not mentioned in devicetree.cb!\n");
  41                 // Trying to set somewhat safe defaults instead of bailing out.
  42                 enable_primary = enable_secondary = 1;
  43         } else {
  44                 enable_primary = config->ide_enable_primary;
  45                 enable_secondary = config->ide_enable_secondary;
  46         }
  47
  48         reg32 = pci_read_config32(dev, PCI_COMMAND);
  49         pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_IO | PCI_COMMAND_MASTER);
  50
  51         /* Native Capable, but not enabled. */
  52         pci_write_config8(dev, 0x09, 0x8a);
  53
  54         ideTimingConfig = pci_read_config16(dev, IDE_TIM_PRI);
  55         ideTimingConfig &= ~IDE_DECODE_ENABLE;
  56         ideTimingConfig |= IDE_SITRE;
  57         if (enable_primary) {
  58                 /* Enable primary IDE interface. */
  59                 ideTimingConfig |= IDE_DECODE_ENABLE;
  60                 ideTimingConfig |= (2 << 12); // ISP = 3 clocks
  61                 ideTimingConfig |= (3 << 8); // RCT = 1 clock
  62                 ideTimingConfig |= (1 << 1); // IE0
  63                 ideTimingConfig |= (1 << 0); // TIME0
  64                 printk(BIOS_DEBUG, "IDE0 ");
  65         }
  66         pci_write_config16(dev, IDE_TIM_PRI, ideTimingConfig);
  67
  68         ideTimingConfig = pci_read_config16(dev, IDE_TIM_SEC);
  69         ideTimingConfig &= ~IDE_DECODE_ENABLE;
  70         ideTimingConfig |= IDE_SITRE;
  71         if (enable_secondary) {
  72                 /* Enable secondary IDE interface. */
  73                 ideTimingConfig |= IDE_DECODE_ENABLE;
  74                 ideTimingConfig |= (2 << 12); // ISP = 3 clocks
  75                 ideTimingConfig |= (3 << 8); // RCT = 1 clock
  76                 ideTimingConfig |= (1 << 1); // IE0
  77                 ideTimingConfig |= (1 << 0); // TIME0
  78                 printk(BIOS_DEBUG, "IDE1 ");
  79         }
  80         pci_write_config16(dev, IDE_TIM_SEC, ideTimingConfig);
  81
  82         /* Set IDE I/O Configuration */
  83         reg32 = 0;
  84         /* FIXME: only set FAST_* for ata/100, only ?CBx for ata/66 */
  85         if (enable_primary)
  86                 reg32 |= SIG_MODE_PRI_NORMAL | FAST_PCB0 | PCB0 | FAST_PCB1 | PCB1;
  87         if (enable_secondary)
  88                 reg32 |= SIG_MODE_SEC_NORMAL | FAST_SCB0 | SCB0 | FAST_SCB1 | SCB1;
  89         pci_write_config32(dev, IDE_CONFIG, reg32);
  90
  91         /* Set Interrupt Line */
  92         /* Interrupt Pin is set by D31IP.PIP */
  93         pci_write_config32(dev, INTR_LN, 0xff); /* Int 15 */
  94
  95         printk(BIOS_DEBUG, "\n");
  96 }
  97
  98 static void ide_set_subsystem(device_t dev, unsigned vendor, unsigned device)
  99 {
 100         if (!vendor || !device) {
 101                 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
 102                                 pci_read_config32(dev, PCI_VENDOR_ID));
 103         } else {
 104                 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
 105                                 ((device & 0xffff) << 16) | (vendor & 0xffff));
 106         }
 107 }
 108
 109 static struct pci_operations ide_pci_ops = {
 110         .set_subsystem    = ide_set_subsystem,
 111 };
 112
 113 static struct device_operations ide_ops = {
 114         .read_resources         = pci_dev_read_resources,
 115         .set_resources          = pci_dev_set_resources,
 116         .enable_resources       = pci_dev_enable_resources,
 117         .init                   = ide_init,
 118         .scan_bus               = 0,
 119         .enable                 = i82801gx_enable,
 120         .ops_pci                = &ide_pci_ops,
 121 };
 122
 123 /* 82801GB/GR/GDH/GBM/GHM/GU (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH/ICH7-U) */
 124 static const struct pci_driver i82801gx_ide __pci_driver = {
 125         .ops    = &ide_ops,
 126         .vendor = PCI_VENDOR_ID_INTEL,
 127         .device = 0x27df,
 128 };