2 * This file is part of the coreboot project.
4 * Copyright (C) 2008 Advanced Micro Devices, Inc.
5 * Copyright (C) 2008-2009 coresystems GmbH
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <console/console.h>
22 #include <device/device.h>
23 #include <device/pci.h>
24 #include <device/pci_ids.h>
25 #include <device/pci_ops.h>
30 #define HDA_ICII_REG 0x68
31 #define HDA_ICII_BUSY (1 << 0)
32 #define HDA_ICII_VALID (1 << 1)
34 typedef struct southbridge_intel_i82801gx_config config_t;
36 static int set_bits(u32 port, u32 mask, u32 val)
41 /* Write (val & mask) to port */
48 /* Wait for readback of register to
49 * match what was just written to it
53 /* Wait 1ms based on BKDG wait time */
57 } while ((reg32 != val) && --count);
65 static int codec_detect(u32 base)
69 /* Set Bit0 to 0 to enter reset state (BAR + 0x8)[0] */
70 if (set_bits(base + 0x08, 1, 0) == -1)
73 /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
74 if (set_bits(base + 0x08, 1, 1) == -1)
77 /* Read in Codec location (BAR + 0xe)[2..0]*/
78 reg32 = read32(base + 0xe);
87 /* Put HDA back in reset (BAR + 0x8) [0] */
88 set_bits(base + 0x08, 1, 0);
89 printk(BIOS_DEBUG, "Azalia: No codec!\n");
93 u32 * cim_verb_data = NULL;
94 u32 cim_verb_data_size = 0;
96 static u32 find_verb(struct device *dev, u32 viddid, u32 ** verb)
100 while (idx < (cim_verb_data_size / sizeof(u32))) {
101 u32 verb_size = 4 * cim_verb_data[idx+2]; // in u32
102 if (cim_verb_data[idx] != viddid) {
103 idx += verb_size + 3; // skip verb + header
106 *verb = &cim_verb_data[idx+3];
110 /* Not all codecs need to load another verb */
115 * Wait 50usec for for the codec to indicate it is ready
116 * no response would imply that the codec is non-operative
119 static int wait_for_ready(u32 base)
121 /* Use a 50 usec timeout - the Linux kernel uses the
127 u32 reg32 = read32(base + HDA_ICII_REG);
128 if (!(reg32 & HDA_ICII_BUSY))
137 * Wait 50usec for for the codec to indicate that it accepted
138 * the previous command. No response would imply that the code
142 static int wait_for_valid(u32 base)
146 /* Send the verb to the codec */
147 reg32 = read32(base + 0x68);
148 reg32 |= (1 << 0) | (1 << 1);
149 write32(base + 0x68, reg32);
151 /* Use a 50 usec timeout - the Linux kernel uses the
156 reg32 = read32(base + HDA_ICII_REG);
157 if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
166 static void codec_init(struct device *dev, u32 base, int addr)
173 printk(BIOS_DEBUG, "Azalia: Initializing codec #%d\n", addr);
176 if (wait_for_ready(base) == -1)
179 reg32 = (addr << 28) | 0x000f0000;
180 write32(base + 0x60, reg32);
182 if (wait_for_valid(base) == -1)
185 reg32 = read32(base + 0x64);
188 printk(BIOS_DEBUG, "Azalia: codec viddid: %08x\n", reg32);
189 verb_size = find_verb(dev, reg32, &verb);
192 printk(BIOS_DEBUG, "Azalia: No verb!\n");
195 printk(BIOS_DEBUG, "Azalia: verb_size: %d\n", verb_size);
198 for (i = 0; i < verb_size; i++) {
199 if (wait_for_ready(base) == -1)
202 write32(base + 0x60, verb[i]);
204 if (wait_for_valid(base) == -1)
207 printk(BIOS_DEBUG, "Azalia: verb loaded.\n");
210 static void codecs_init(struct device *dev, u32 base, u32 codec_mask)
213 for (i = 2; i >= 0; i--) {
214 if (codec_mask & (1 << i))
215 codec_init(dev, base, i);
219 static void azalia_init(struct device *dev)
222 struct resource *res;
227 #if CONFIG_MMCONF_SUPPORT
229 reg32 = pci_mmio_read_config32(dev, 0x134);
232 pci_mmio_write_config32(dev, 0x134, reg32);
235 reg32 = pci_mmio_read_config32(dev, 0x140);
238 pci_mmio_write_config32(dev, 0x140, reg32);
240 // Port VC0 Resource Control Register
241 reg32 = pci_mmio_read_config32(dev, 0x114);
244 pci_mmio_write_config32(dev, 0x114, reg32);
247 reg8 = pci_mmio_read_config8(dev, 0x44);
248 reg8 |= (7 << 0); // TC7
249 pci_mmio_write_config8(dev, 0x44, reg8);
251 // VCi Resource Control
252 reg32 = pci_mmio_read_config32(dev, 0x120);
254 reg32 |= (1 << 24); // VCi ID
255 reg32 |= (0x80 << 0); // VCi map
256 pci_mmio_write_config32(dev, 0x120, reg32);
258 #error ICH7 Azalia required CONFIG_MMCONF_SUPPORT
262 reg32 = pci_read_config32(dev, PCI_COMMAND);
263 pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);
265 pci_write_config8(dev, 0x3c, 0x0a); // unused?
267 // TODO Actually check if we're AC97 or HDA instead of hardcoding this
268 // here, in devicetree.cb and/or romstage.c.
269 reg8 = pci_read_config8(dev, 0x40);
270 reg8 |= (1 << 3); // Clear Clock Detect Bit
271 pci_write_config8(dev, 0x40, reg8);
272 reg8 &= ~(1 << 3); // Keep CLKDETCLR from clearing the bit over and over
273 pci_write_config8(dev, 0x40, reg8);
274 reg8 |= (1 << 2); // Enable clock detection
275 pci_write_config8(dev, 0x40, reg8);
277 reg8 = pci_read_config8(dev, 0x40);
278 printk(BIOS_DEBUG, "Azalia: codec type: %s\n", (reg8 & (1 << 1))?"Azalia":"AC97");
281 reg8 = pci_read_config8(dev, 0x40); // Audio Control
282 reg8 |= 1; // Select Azalia mode. This needs to be controlled via devicetree.cb
283 pci_write_config8(dev, 0x40, reg8);
285 reg8 = pci_read_config8(dev, 0x4d); // Docking Status
286 reg8 &= ~(1 << 7); // Docking not supported
287 pci_write_config8(dev, 0x4d, reg8);
289 /* Set routing pin */
290 pci_write_config32(dev, 0xf8, 0x0);
291 pci_write_config8(dev, 0xfc, 0xAA);
294 pci_write_config8(dev, 0x63, 0x0);
296 /* Enable azalia, disable ac97 */
297 // pm_iowrite(0x59, 0xB);
300 res = find_resource(dev, 0x10);
304 // NOTE this will break as soon as the Azalia get's a bar above
305 // 4G. Is there anything we can do about it?
306 base = (u32)res->base;
307 printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base);
308 codec_mask = codec_detect(base);
311 printk(BIOS_DEBUG, "Azalia: codec_mask = %02x\n", codec_mask);
312 codecs_init(dev, base, codec_mask);
316 static void azalia_set_subsystem(device_t dev, unsigned vendor, unsigned device)
318 if (!vendor || !device) {
319 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
320 pci_read_config32(dev, PCI_VENDOR_ID));
322 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
323 ((device & 0xffff) << 16) | (vendor & 0xffff));
327 static struct pci_operations azalia_pci_ops = {
328 .set_subsystem = azalia_set_subsystem,
331 static struct device_operations azalia_ops = {
332 .read_resources = pci_dev_read_resources,
333 .set_resources = pci_dev_set_resources,
334 .enable_resources = pci_dev_enable_resources,
337 .enable = i82801gx_enable,
338 .ops_pci = &azalia_pci_ops,
341 /* 82801GB/GR/GDH/GBM/GHM (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH) */
342 static const struct pci_driver i82801gx_azalia __pci_driver = {
344 .vendor = PCI_VENDOR_ID_INTEL,