2 * This file is part of the coreboot project.
4 * Copyright (C) 2008-2009 coresystems GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #ifndef SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H
22 #define SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H
24 * It does not matter where we put the SMBus I/O base, as long as we
25 * keep it consistent and don't interfere with other devices. Stage2
26 * will relocate this anyways.
27 * Our solution is to have SMB initialization move the I/O to SMBUS_IO_BASE
28 * again. But handling static BARs is a generic problem that should be
29 * solved in the device allocator.
31 #define SMBUS_IO_BASE 0x0400
32 /* TODO Make sure these don't get changed by stage2 */
33 #define DEFAULT_GPIOBASE 0x0480
34 #define DEFAULT_PMBASE 0x0500
35 #define HPET_ADDR 0xfed00000
36 #define DEFAULT_RCBA 0xfed1c000
39 #define DEBUG_PERIODIC_SMIS 0
41 /* __ROMCC__ is set by auto.c to make sure
42 * none of the stage2 data structures are included.
46 extern void i82801gx_enable(device_t dev);
49 /* PCI Configuration Space (D31:F0): LPC */
51 #define SERIRQ_CNTL 0x64
53 #define GEN_PMCON_1 0xa0
54 #define GEN_PMCON_2 0xa2
55 #define GEN_PMCON_3 0xa4
57 /* GEN_PMCON_3 bits */
58 #define RTC_BATTERY_DEAD (1 << 2)
59 #define RTC_POWER_FAILED (1 << 1)
60 #define SLEEP_AFTER_POWER_FAIL (1 << 0)
63 #define ACPI_CNTL 0x44
64 #define BIOS_CNTL 0xDC
65 #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */
66 #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */
68 #define PIRQA_ROUT 0x60
69 #define PIRQB_ROUT 0x61
70 #define PIRQC_ROUT 0x62
71 #define PIRQD_ROUT 0x63
72 #define PIRQE_ROUT 0x68
73 #define PIRQF_ROUT 0x69
74 #define PIRQG_ROUT 0x6A
75 #define PIRQH_ROUT 0x6B
77 #define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */
78 #define LPC_EN 0x82 /* LPC IF Enables Register */
80 /* PCI Configuration Space (D31:F1): IDE */
82 #define IDE_TIM_PRI 0x40 /* IDE timings, primary */
83 #define IDE_DECODE_ENABLE (1 << 15)
84 #define IDE_SITRE (1 << 14)
85 #define IDE_ISP_5_CLOCKS (0 << 12)
86 #define IDE_ISP_4_CLOCKS (1 << 12)
87 #define IDE_ISP_3_CLOCKS (2 << 12)
88 #define IDE_RCT_4_CLOCKS (0 << 8)
89 #define IDE_RCT_3_CLOCKS (1 << 8)
90 #define IDE_RCT_2_CLOCKS (2 << 8)
91 #define IDE_RCT_1_CLOCKS (3 << 8)
92 #define IDE_DTE1 (1 << 7)
93 #define IDE_PPE1 (1 << 6)
94 #define IDE_IE1 (1 << 5)
95 #define IDE_TIME1 (1 << 4)
96 #define IDE_DTE0 (1 << 3)
97 #define IDE_PPE0 (1 << 2)
98 #define IDE_IE0 (1 << 1)
99 #define IDE_TIME0 (1 << 0)
100 #define IDE_TIM_SEC 0x42 /* IDE timings, secondary */
102 #define IDE_SDMA_CNT 0x48 /* Synchronous DMA control */
103 #define IDE_SSDE1 (1 << 3)
104 #define IDE_SSDE0 (1 << 2)
105 #define IDE_PSDE1 (1 << 1)
106 #define IDE_PSDE0 (1 << 0)
108 #define IDE_SDMA_TIM 0x4a
110 #define IDE_CONFIG 0x54 /* IDE I/O Configuration Register */
111 #define SIG_MODE_SEC_NORMAL (0 << 18)
112 #define SIG_MODE_SEC_TRISTATE (1 << 18)
113 #define SIG_MODE_SEC_DRIVELOW (2 << 18)
114 #define SIG_MODE_PRI_NORMAL (0 << 16)
115 #define SIG_MODE_PRI_TRISTATE (1 << 16)
116 #define SIG_MODE_PRI_DRIVELOW (2 << 16)
117 #define FAST_SCB1 (1 << 15)
118 #define FAST_SCB0 (1 << 14)
119 #define FAST_PCB1 (1 << 13)
120 #define FAST_PCB0 (1 << 12)
121 #define SCB1 (1 << 3)
122 #define SCB0 (1 << 2)
123 #define PCB1 (1 << 1)
124 #define PCB0 (1 << 0)
126 /* PCI Configuration Space (D31:F3): SMBus */
127 #define SMB_BASE 0x20
131 #define I2C_EN (1 << 2)
132 #define SMB_SMI_EN (1 << 1)
133 #define HST_EN (1 << 0)
135 /* SMBus I/O bits. */
136 #define SMBHSTSTAT 0x0
137 #define SMBHSTCTL 0x2
138 #define SMBHSTCMD 0x3
139 #define SMBXMITADD 0x4
140 #define SMBHSTDAT0 0x5
141 #define SMBHSTDAT1 0x6
142 #define SMBBLKDAT 0x7
143 #define SMBTRNSADD 0x9
144 #define SMBSLVDATA 0xa
145 #define SMLINK_PIN_CTL 0xe
146 #define SMBUS_PIN_CTL 0xf
148 #define SMBUS_TIMEOUT (10 * 1000 * 100)
151 /* Southbridge IO BARs */
153 #define GPIOBASE 0x48
157 /* Root Complex Register Block */
160 #define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x))
161 #define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x))
162 #define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x))
164 #define VCH 0x0000 /* 32bit */
165 #define VCAP1 0x0004 /* 32bit */
166 #define VCAP2 0x0008 /* 32bit */
167 #define PVC 0x000c /* 16bit */
168 #define PVS 0x000e /* 16bit */
170 #define V0CAP 0x0010 /* 32bit */
171 #define V0CTL 0x0014 /* 32bit */
172 #define V0STS 0x001a /* 16bit */
174 #define V1CAP 0x001c /* 32bit */
175 #define V1CTL 0x0020 /* 32bit */
176 #define V1STS 0x0026 /* 16bit */
178 #define RCTCL 0x0100 /* 32bit */
179 #define ESD 0x0104 /* 32bit */
180 #define ULD 0x0110 /* 32bit */
181 #define ULBA 0x0118 /* 64bit */
183 #define RP1D 0x0120 /* 32bit */
184 #define RP1BA 0x0128 /* 64bit */
185 #define RP2D 0x0130 /* 32bit */
186 #define RP2BA 0x0138 /* 64bit */
187 #define RP3D 0x0140 /* 32bit */
188 #define RP3BA 0x0148 /* 64bit */
189 #define RP4D 0x0150 /* 32bit */
190 #define RP4BA 0x0158 /* 64bit */
191 #define HDD 0x0160 /* 32bit */
192 #define HDBA 0x0168 /* 64bit */
193 #define RP5D 0x0170 /* 32bit */
194 #define RP5BA 0x0178 /* 64bit */
195 #define RP6D 0x0180 /* 32bit */
196 #define RP6BA 0x0188 /* 64bit */
198 #define ILCL 0x01a0 /* 32bit */
199 #define LCAP 0x01a4 /* 32bit */
200 #define LCTL 0x01a8 /* 16bit */
201 #define LSTS 0x01aa /* 16bit */
203 #define RPC 0x0224 /* 32bit */
204 #define RPFN 0x0238 /* 32bit */
206 #define TRSR 0x1e00 /* 8bit */
207 #define TRCR 0x1e10 /* 64bit */
208 #define TWDR 0x1e18 /* 64bit */
210 #define IOTR0 0x1e80 /* 64bit */
211 #define IOTR1 0x1e88 /* 64bit */
212 #define IOTR2 0x1e90 /* 64bit */
213 #define IOTR3 0x1e98 /* 64bit */
215 #define TCTL 0x3000 /* 8bit */
217 #define D31IP 0x3100 /* 32bit */
218 #define D30IP 0x3104 /* 32bit */
219 #define D29IP 0x3108 /* 32bit */
220 #define D28IP 0x310c /* 32bit */
221 #define D27IP 0x3110 /* 32bit */
222 #define D31IR 0x3140 /* 16bit */
223 #define D30IR 0x3142 /* 16bit */
224 #define D29IR 0x3144 /* 16bit */
225 #define D28IR 0x3146 /* 16bit */
226 #define D27IR 0x3148 /* 16bit */
227 #define OIC 0x31ff /* 8bit */
229 #define RC 0x3400 /* 32bit */
230 #define HPTC 0x3404 /* 32bit */
231 #define GCS 0x3410 /* 32bit */
232 #define BUC 0x3414 /* 32bit */
233 #define FD 0x3418 /* 32bit */
234 #define CG 0x341c /* 32bit */
236 /* Function Disable (FD) register values.
237 * Setting a bit disables the corresponding
239 * Not all features might be disabled on
240 * all chipsets. Esp. ICH-7U is picky.
242 #define FD_PCIE6 (1 << 21)
243 #define FD_PCIE5 (1 << 20)
244 #define FD_PCIE4 (1 << 19)
245 #define FD_PCIE3 (1 << 18)
246 #define FD_PCIE2 (1 << 17)
247 #define FD_PCIE1 (1 << 16)
248 #define FD_EHCI (1 << 15)
249 #define FD_LPCB (1 << 14)
251 /* UHCI must be disabled from 4 downwards.
252 * If UHCI controllers get disabled, EHCI
253 * must know about it, too! */
254 #define FD_UHCI4 (1 << 11)
255 #define FD_UHCI34 (1 << 10) | FD_UHCI4
256 #define FD_UHCI234 (1 << 9) | FD_UHCI3
257 #define FD_UHCI1234 (1 << 8) | FD_UHCI2
259 #define FD_INTLAN (1 << 7)
260 #define FD_ACMOD (1 << 6)
261 #define FD_ACAUD (1 << 5)
262 #define FD_HDAUD (1 << 4)
263 #define FD_SMBUS (1 << 3)
264 #define FD_SATA (1 << 2)
265 #define FD_PATA (1 << 1)
268 #define GPIO_USE_SEL 0x00
269 #define GP_IO_SEL 0x04
271 #define GPO_BLINK 0x18
273 #define GPIO_USE_SEL2 0x30
274 #define GP_IO_SEL2 0x34
281 #define SLP_EN (1 << 13)
282 #define SLP_TYP (7 << 10)
283 #define GBL_RLS (1 << 2)
284 #define BM_RLD (1 << 1)
285 #define SCI_EN (1 << 0)
287 #define PROC_CNT 0x10
291 #define PM2_CNT 0x20 // mobile only
292 #define GPE0_STS 0x28
294 #define PME_B0_EN (1 << 13)
296 #define EL_SMI_EN (1 << 25) // Intel Quick Resume Technology
297 #define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic
298 #define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic
299 #define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS
300 #define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al)
301 #define MCSMI_EN (1 << 11) // Trap microcontroller range access
302 #define BIOS_RLS (1 << 7) // asserts SCI on bit set
303 #define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set
304 #define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI#
305 #define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI#
306 #define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic
307 #define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit
308 #define EOS (1 << 1) // End of SMI (deassert SMI#)
309 #define GBL_SMI_EN (1 << 0) // SMI# generation at all?
311 #define ALT_GP_SMI_EN 0x38
312 #define ALT_GP_SMI_STS 0x3a
313 #define GPE_CNTL 0x42
314 #define DEVACT_STS 0x44
318 #endif /* __ACPI__ */
319 #endif /* SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H */