2 * This file is part of the coreboot project.
4 * Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <arch/romcc_io.h>
23 static void enable_spi_prefetch(void)
28 dev = PCI_DEV(0, 0x1f, 0);
30 reg8 = pci_read_config8(dev, 0xdc);
32 reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
33 pci_write_config8(dev, 0xdc, reg8);
36 static void bootblock_southbridge_init(void)
38 enable_spi_prefetch();