1 #include "i82801ex_smbus.h"
3 #define SMBUS_IO_BASE 0x0f00
5 static void enable_smbus(void)
7 device_t dev = PCI_DEV(0x0, 0x1f, 0x3);
9 print_spew("SMBus controller enabled\n");
11 pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1);
12 print_debug_hex32(pci_read_config32(dev, 0x20));
13 /* Set smbus enable */
14 pci_write_config8(dev, 0x40, 1);
15 /* Set smbus iospace enable */
16 pci_write_config8(dev, 0x4, 1);
18 pci_write_config8(dev, 0x11, 4);
20 /* Disable interrupt generation */
21 outb(0, SMBUS_IO_BASE + SMBHSTCTL);
23 /* clear any lingering errors, so the transaction will run */
24 outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
27 static int smbus_read_byte(unsigned device, unsigned address)
29 return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
33 static void smbus_write_byte(unsigned device, unsigned address, unsigned char val)
35 if (smbus_wait_until_ready(SMBUS_IO_BASE) < 0) {
39 print_debug("Unimplemented smbus_write_byte() called.\n");
42 /* setup transaction */
43 /* disable interrupts */
44 outw(inw(SMBUS_IO_BASE + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)),
45 SMBUS_IO_BASE + SMBGCTL);
46 /* set the device I'm talking too */
47 outw(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBHSTADDR);
48 outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
49 /* set up for a byte data write */ /* FIXME */
50 outw((inw(SMBUS_IO_BASE + SMBGCTL) & ~7) | (0x1), SMBUS_IO_BASE + SMBGCTL);
51 /* clear any lingering errors, so the transaction will run */
52 /* Do I need to write the bits to a 1 to clear an error? */
53 outw(inw(SMBUS_IO_BASE + SMBGSTATUS), SMBUS_IO_BASE + SMBGSTATUS);
55 /* clear the data word...*/
56 outw(val, SMBUS_IO_BASE + SMBHSTDAT);
58 /* start the command */
59 outw((inw(SMBUS_IO_BASE + SMBGCTL) | (1 << 3)), SMBUS_IO_BASE + SMBGCTL);
61 /* poll for transaction completion */
62 smbus_wait_until_done(SMBUS_IO_BASE);
67 static int smbus_write_block(unsigned device, unsigned length, unsigned cmd,
68 unsigned data1, unsigned data2)
74 /* chear the PM timeout flags, SECOND_TO_STS */
75 outw(inw(0x0400 + 0x66), 0x0400 + 0x66);
77 if (smbus_wait_until_ready(SMBUS_IO_BASE) < 0) {
81 /* setup transaction */
82 /* Obtain ownership */
83 outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
84 for(stat=0;(stat&0x40)==0;) {
85 stat = inb(SMBUS_IO_BASE + SMBHSTSTAT);
87 /* clear the done bit */
88 outb(0x80, SMBUS_IO_BASE + SMBHSTSTAT);
89 /* disable interrupts */
90 outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL);
92 /* set the device I'm talking too */
93 outb(((device & 0x7f) << 1), SMBUS_IO_BASE + SMBXMITADD);
95 /* set the command address */
96 outb(cmd & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
98 /* set the block length */
99 outb(length & 0xFF, SMBUS_IO_BASE + SMBHSTDAT0);
101 /* try sending out the first byte of data here */
102 byte=(data1>>(0))&0x0ff;
103 outb(byte,SMBUS_IO_BASE + SMBBLKDAT);
104 /* issue a block write command */
105 outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x5 << 2) | 0x40,
106 SMBUS_IO_BASE + SMBHSTCTL);
108 for(i=0;i<length;i++) {
110 /* poll for transaction completion */
111 if (smbus_wait_until_blk_done(SMBUS_IO_BASE) < 0) {
115 /* load the next byte */
117 byte=(data2>>(i%4))&0x0ff;
119 byte=(data1>>(i))&0x0ff;
120 outb(byte,SMBUS_IO_BASE + SMBBLKDAT);
122 /* clear the done bit */
123 outb(inb(SMBUS_IO_BASE + SMBHSTSTAT),
124 SMBUS_IO_BASE + SMBHSTSTAT);
127 print_debug("SMBUS Block complete\n");