2 * This file is part of the coreboot project.
4 * Copyright (C) 2008-2009 coresystems GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
23 #include <device/device.h>
24 #include <device/pci.h>
25 #include <console/console.h>
28 #include <cpu/x86/cache.h>
29 #include <cpu/x86/smm.h>
33 extern unsigned char smm[];
34 extern unsigned int smm_len;
38 #define D_OPEN (1 << 6)
39 #define D_CLS (1 << 5)
40 #define D_LCK (1 << 4)
41 #define G_SMRAME (1 << 3)
42 #define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
44 /* While we read PMBASE dynamically in case it changed, let's
45 * initialize it with a sane value
47 static u16 pmbase = PMBASE_ADDR;
50 * @brief read and clear PM1_STS
51 * @return PM1_STS register
53 static u16 reset_pm1_status(void)
57 reg16 = inw(pmbase + PM1_STS);
58 /* set status bits are cleared by writing 1 to them */
59 outw(reg16, pmbase + PM1_STS);
64 static void dump_pm1_status(u16 pm1_sts)
66 printk_debug("PM1_STS: ");
67 if (pm1_sts & (1 << 15)) printk_debug("WAK ");
68 if (pm1_sts & (1 << 14)) printk_debug("PCIEXPWAK ");
69 if (pm1_sts & (1 << 11)) printk_debug("PRBTNOR ");
70 if (pm1_sts & (1 << 10)) printk_debug("RTC ");
71 if (pm1_sts & (1 << 8)) printk_debug("PWRBTN ");
72 if (pm1_sts & (1 << 5)) printk_debug("GBL ");
73 if (pm1_sts & (1 << 4)) printk_debug("BM ");
74 if (pm1_sts & (1 << 0)) printk_debug("TMROF ");
79 * @brief read and clear SMI_STS
80 * @return SMI_STS register
82 static u32 reset_smi_status(void)
86 reg32 = inl(pmbase + SMI_STS);
87 /* set status bits are cleared by writing 1 to them */
88 outl(reg32, pmbase + SMI_STS);
93 static void dump_smi_status(u32 smi_sts)
95 printk_debug("SMI_STS: ");
96 if (smi_sts & (1 << 26)) printk_debug("SPI ");
97 if (smi_sts & (1 << 25)) printk_debug("EL_SMI ");
98 if (smi_sts & (1 << 21)) printk_debug("MONITOR ");
99 if (smi_sts & (1 << 20)) printk_debug("PCI_EXP_SMI ");
100 if (smi_sts & (1 << 18)) printk_debug("INTEL_USB2 ");
101 if (smi_sts & (1 << 17)) printk_debug("LEGACY_USB2 ");
102 if (smi_sts & (1 << 16)) printk_debug("SMBUS_SMI ");
103 if (smi_sts & (1 << 15)) printk_debug("SERIRQ_SMI ");
104 if (smi_sts & (1 << 14)) printk_debug("PERIODIC ");
105 if (smi_sts & (1 << 13)) printk_debug("TCO ");
106 if (smi_sts & (1 << 12)) printk_debug("DEVMON ");
107 if (smi_sts & (1 << 11)) printk_debug("MCSMI ");
108 if (smi_sts & (1 << 10)) printk_debug("GPI ");
109 if (smi_sts & (1 << 9)) printk_debug("GPE0 ");
110 if (smi_sts & (1 << 8)) printk_debug("PM1 ");
111 if (smi_sts & (1 << 6)) printk_debug("SWSMI_TMR ");
112 if (smi_sts & (1 << 5)) printk_debug("APM ");
113 if (smi_sts & (1 << 4)) printk_debug("SLP_SMI ");
114 if (smi_sts & (1 << 3)) printk_debug("LEGACY_USB ");
115 if (smi_sts & (1 << 2)) printk_debug("BIOS ");
121 * @brief read and clear GPE0_STS
122 * @return GPE0_STS register
124 static u32 reset_gpe0_status(void)
128 reg32 = inl(pmbase + GPE0_STS);
129 /* set status bits are cleared by writing 1 to them */
130 outl(reg32, pmbase + GPE0_STS);
135 static void dump_gpe0_status(u32 gpe0_sts)
138 printk_debug("GPE0_STS: ");
139 for (i=31; i<= 16; i--) {
140 if (gpe0_sts & (1 << i)) printk_debug("GPIO%d ", (i-16));
142 if (gpe0_sts & (1 << 14)) printk_debug("USB4 ");
143 if (gpe0_sts & (1 << 13)) printk_debug("PME_B0 ");
144 if (gpe0_sts & (1 << 12)) printk_debug("USB3 ");
145 if (gpe0_sts & (1 << 11)) printk_debug("PME ");
146 if (gpe0_sts & (1 << 10)) printk_debug("EL_SCI/BATLOW ");
147 if (gpe0_sts & (1 << 9)) printk_debug("PCI_EXP ");
148 if (gpe0_sts & (1 << 8)) printk_debug("RI ");
149 if (gpe0_sts & (1 << 7)) printk_debug("SMB_WAK ");
150 if (gpe0_sts & (1 << 6)) printk_debug("TCO_SCI ");
151 if (gpe0_sts & (1 << 5)) printk_debug("AC97 ");
152 if (gpe0_sts & (1 << 4)) printk_debug("USB2 ");
153 if (gpe0_sts & (1 << 3)) printk_debug("USB1 ");
154 if (gpe0_sts & (1 << 2)) printk_debug("HOT_PLUG ");
155 if (gpe0_sts & (1 << 0)) printk_debug("THRM ");
161 * @brief read and clear ALT_GP_SMI_STS
162 * @return ALT_GP_SMI_STS register
164 static u16 reset_alt_gp_smi_status(void)
168 reg16 = inl(pmbase + ALT_GP_SMI_STS);
169 /* set status bits are cleared by writing 1 to them */
170 outl(reg16, pmbase + ALT_GP_SMI_STS);
175 static void dump_alt_gp_smi_status(u16 alt_gp_smi_sts)
178 printk_debug("ALT_GP_SMI_STS: ");
179 for (i=15; i<= 0; i--) {
180 if (alt_gp_smi_sts & (1 << i)) printk_debug("GPI%d ", (i-16));
188 * @brief read and clear TCOx_STS
189 * @return TCOx_STS registers
191 static u32 reset_tco_status(void)
193 u32 tcobase = pmbase + 0x60;
196 reg32 = inl(tcobase + 0x04);
197 /* set status bits are cleared by writing 1 to them */
198 outl(reg32 & ~(1<<18), tcobase + 0x04); // Don't clear BOOT_STS before SECOND_TO_STS
199 if (reg32 & (1 << 18))
200 outl(reg32 & (1<<18), tcobase + 0x04); // clear BOOT_STS
206 static void dump_tco_status(u32 tco_sts)
208 printk_debug("TCO_STS: ");
209 if (tco_sts & (1 << 20)) printk_debug("SMLINK_SLV ");
210 if (tco_sts & (1 << 18)) printk_debug("BOOT ");
211 if (tco_sts & (1 << 17)) printk_debug("SECOND_TO ");
212 if (tco_sts & (1 << 16)) printk_debug("INTRD_DET ");
213 if (tco_sts & (1 << 12)) printk_debug("DMISERR ");
214 if (tco_sts & (1 << 10)) printk_debug("DMISMI ");
215 if (tco_sts & (1 << 9)) printk_debug("DMISCI ");
216 if (tco_sts & (1 << 8)) printk_debug("BIOSWR ");
217 if (tco_sts & (1 << 7)) printk_debug("NEWCENTURY ");
218 if (tco_sts & (1 << 3)) printk_debug("TIMEOUT ");
219 if (tco_sts & (1 << 2)) printk_debug("TCO_INT ");
220 if (tco_sts & (1 << 1)) printk_debug("SW_TCO ");
221 if (tco_sts & (1 << 0)) printk_debug("NMI2SMI ");
228 * @brief Set the EOS bit
230 static void smi_set_eos(void)
234 reg8 = inb(pmbase + SMI_EN);
236 outb(reg8, pmbase + SMI_EN);
239 extern uint8_t smm_relocation_start, smm_relocation_end;
241 static void smm_relocate(void)
246 printk_debug("Initializing SMM handler...");
248 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), 0x40) & 0xfffc;
249 printk_spew(" ... pmbase = 0x%04x\n", pmbase);
251 smi_en = inl(pmbase + SMI_EN);
252 if (smi_en & APMC_EN) {
253 printk_info("SMI# handler already enabled?\n");
257 /* copy the SMM relocation code */
258 memcpy((void *)0x38000, &smm_relocation_start,
259 &smm_relocation_end - &smm_relocation_start);
262 dump_smi_status(reset_smi_status());
263 dump_pm1_status(reset_pm1_status());
264 dump_gpe0_status(reset_gpe0_status());
265 dump_alt_gp_smi_status(reset_alt_gp_smi_status());
266 dump_tco_status(reset_tco_status());
268 /* Enable SMI generation:
270 * - on APMC writes (io 0xb2)
271 * - on writes to SLP_EN (sleep states)
272 * - on writes to GBL_RLS (bios commands)
274 * - on microcontroller writes (io 0x62/0x66)
277 smi_en = 0; /* reset SMI enables */
280 smi_en |= LEGACY_USB2_EN | LEGACY_USB_EN;
284 #if DEBUG_PERIODIC_SMIS
285 /* Set DEBUG_PERIODIC_SMIS in i82801gx.h to debug using
288 smi_en |= PERIODIC_EN;
290 smi_en |= SLP_SMI_EN;
293 /* The following need to be on for SMIs to happen */
294 smi_en |= EOS | GBL_SMI_EN;
296 outl(smi_en, pmbase + SMI_EN);
301 outw(pm1_en, pmbase + PM1_EN);
304 * There are several methods of raising a controlled SMI# via
305 * software, among them:
306 * - Writes to io 0xb2 (APMC)
307 * - Writes to the Local Apic ICR with Delivery mode SMI.
309 * Using the local apic is a bit more tricky. According to
310 * AMD Family 11 Processor BKDG no destination shorthand must be
312 * The whole SMM initialization is quite a bit hardware specific, so
313 * I'm not too worried about the better of the methods at the moment
316 /* raise an SMI interrupt */
317 printk_spew(" ... raise SMI#\n");
321 static void smm_install(void)
323 /* enable the SMM memory window */
324 pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM,
325 D_OPEN | G_SMRAME | C_BASE_SEG);
327 /* copy the real SMM handler */
328 memcpy((void *)0xa0000, smm, smm_len);
331 /* close the SMM memory window and enable normal SMM */
332 pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM,
333 G_SMRAME | C_BASE_SEG);
338 // FIXME is this a race condition?
342 // We're done. Make sure SMIs can happen!
348 /* LOCK the SMM memory window and enable normal SMM.
349 * After running this function, only a full reset can
350 * make the SMM registers writable again.
352 printk_debug("Locking SMM.\n");
353 pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM,
354 D_LCK | G_SMRAME | C_BASE_SEG);
357 void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
359 /* The GDT or coreboot table is going to live here. But a long time
360 * after we relocated the GNVS, so this is not troublesome.
362 *(u32 *)0x500 = (u32)gnvs;
363 *(u32 *)0x504 = (u32)tcg;
364 *(u32 *)0x508 = (u32)smi1;