2 * This file is part of the coreboot project.
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5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
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10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 #include <console/console.h>
20 #include <device/device.h>
21 #include <device/pci.h>
22 #include <device/pci_ids.h>
25 void i82801db_enable(device_t dev)
30 printk_debug("Entering %s\n", __FUNCTION__);
31 /* See if we are behind the i82801db pci bridge
32 lpc_dev = dev_find_slot(dev->bus->secondary, PCI_DEVFN(0x1f, 0));
34 lpc_dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
40 pci_write_config16(lpc_dev, 0xf2, word);
42 if((dev->path.u.pci.devfn &0xf8)== 0xf8) {
43 index = dev->path.u.pci.devfn & 7;
45 else if((dev->path.u.pci.devfn &0xf8)== 0xe8) {
46 index = (dev->path.u.pci.devfn & 7) +8;
49 reg = reg_old = pci_read_config16(lpc_dev, 0xf2);
55 printk_debug("Trying to enable device, [0:1f:0] reg 0xf2 <- %04x\n", reg);
56 pci_write_config16(lpc_dev, 0xf2, reg);
61 struct chip_operations southbridge_intel_i82801db_ops = {
62 CHIP_NAME("Intel 82801DB Southbridge")
63 .enable_dev = i82801db_enable,