1 #include <console/console.h>
2 #include <device/device.h>
3 #include <device/pci.h>
4 #include <device/pci_ids.h>
8 void i82801cx_enable(device_t dev)
10 unsigned int index = 0;
11 uint8_t bHasDisableBit = 0;
12 uint16_t cur_disable_mask, new_disable_mask;
14 // all 82801ca devices are in bus 0
15 unsigned int devfn = PCI_DEVFN(0x1f, 0); // lpc
16 device_t lpc_dev = dev_find_slot(0, devfn); // 0
20 // Calculate disable bit position for specified device:function
21 // NOTE: For ICH-3, only the following devices can be disabled:
22 // D31:F1, D31:F3, D31:F5, D31:F6,
23 // D29:F0, D29:F1, D29:F2
25 if (PCI_SLOT(dev->path.pci.devfn) == 31) {
26 index = PCI_FUNC(dev->path.pci.devfn);
28 if ((index == 1) || (index == 3) || (index == 5) || (index == 6))
31 } else if (PCI_SLOT(dev->path.pci.devfn) == 29) {
32 index = 8 + PCI_FUNC(dev->path.pci.devfn);
34 if (PCI_FUNC(dev->path.pci.devfn) < 3)
39 cur_disable_mask = pci_read_config16(lpc_dev, FUNC_DIS);
40 new_disable_mask = cur_disable_mask & ~(1<<index); // enable it
42 new_disable_mask |= (1<<index); // disable it
44 if (new_disable_mask != cur_disable_mask) {
45 pci_write_config16(lpc_dev, FUNC_DIS, new_disable_mask);
50 struct chip_operations southbridge_intel_i82801cx_ops = {
51 CHIP_NAME("Intel ICH3 (82801Cx) Series Southbridge")
52 .enable_dev = i82801cx_enable,