1 #include <device/pci_ids.h>
4 static void enable_smbus(void)
6 device_t dev = PCI_DEV(0x0, 0x1f, 0x3);
8 print_debug("SMBus controller enabled\n");
10 pci_write_config32(dev, SMB_BASE, SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO);
11 /* Set smbus enable */
12 pci_write_config8(dev, HOSTC, HST_EN);
13 /* Set smbus iospace enable */
14 pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
15 /* Disable interrupt generation */
16 outb(0, SMBUS_IO_BASE + SMBHSTCTL);
17 /* clear any lingering errors, so the transaction will run */
18 outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
22 static inline void smbus_delay(void)
27 // See http://www.coreboot.org/pipermail/linuxbios/2004-September/009077.html
28 // for a description of this function.
29 static int smbus_wait_until_active(void)
32 loops = SMBUS_TIMEOUT;
36 val = inb(SMBUS_IO_BASE + SMBHSTSTAT);
41 return loops ? 0 : -4;
44 static int smbus_wait_until_ready(void)
47 loops = SMBUS_TIMEOUT;
51 val = inb(SMBUS_IO_BASE + SMBHSTSTAT);
56 if(loops == (SMBUS_TIMEOUT / 2)) {
58 outb(inb(SMBUS_IO_BASE + SMBHSTSTAT),
59 SMBUS_IO_BASE + SMBHSTSTAT);
65 static int smbus_wait_until_done(void)
68 loops = SMBUS_TIMEOUT;
73 val = inb(SMBUS_IO_BASE + SMBHSTSTAT);
75 if ( (val & 1) == 0) {
78 // BYTE_DONE or SUCCESS or error?
79 if ((val & ~((1<<6)|(1<<0)) ) != 0 ) {
86 static int smbus_read_byte(unsigned device, unsigned address)
88 unsigned char global_control_register;
89 unsigned char global_status_register;
92 if (smbus_wait_until_ready() < 0) {
96 /* setup transaction */
97 /* disable interrupts */
98 outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xfe, SMBUS_IO_BASE + SMBHSTCTL);
99 /* set to read from the specified device */
100 outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBXMITADD);
101 /* set the command/address... */
102 outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
103 /* set up for a byte data read */
104 outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x2<<2), SMBUS_IO_BASE + SMBHSTCTL);
106 /* clear any lingering errors, so the transaction will run */
107 outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
109 /* clear the data byte...*/
110 outb(0, SMBUS_IO_BASE + SMBHSTDAT0);
112 /* start a byte read, with interrupts disabled */
113 outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), SMBUS_IO_BASE + SMBHSTCTL);
114 /* poll for it to start */
115 if (smbus_wait_until_active() < 0) {
119 /* poll for transaction completion */
120 if (smbus_wait_until_done() < 0) {
124 global_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT) & ~(1<<6); /* Ignore the In Use Status... */
126 /* read results of transaction */
127 byte = inb(SMBUS_IO_BASE + SMBHSTDAT0);
130 if (global_status_register != 2) {