2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #ifndef SOUTHBRIDGE_INTEL_I82801BX_I82801BX_H
22 #define SOUTHBRIDGE_INTEL_I82801BX_I82801BX_H
24 #if !defined(__PRE_RAM__)
26 extern void i82801bx_enable(device_t dev);
29 #define SMBUS_IO_BASE 0x0f00
30 #define PMBASE_ADDR 0x0400
31 #define GPIO_BASE_ADDR 0x0500
32 #define HPET_ADDR 0xfed00000
36 #define PCI_DMA_CFG 0x90
37 #define SERIRQ_CNTL 0x64
41 #define GEN_PMCON_3 0xa4
44 #define ACPI_CNTL 0x44
45 #define ACPI_EN (1 << 4)
46 #define BIOS_CNTL 0x4E
47 #define GPIO_BASE 0x58 /* GPIO Base Address Register */
48 #define GPIO_CNTL 0x5C /* GPIO Control Register */
49 #define GPIO_EN (1 << 4)
51 #define PIRQA_ROUT 0x60
52 #define PIRQB_ROUT 0x61
53 #define PIRQC_ROUT 0x62
54 #define PIRQD_ROUT 0x63
55 #define PIRQE_ROUT 0x68
56 #define PIRQF_ROUT 0x69
57 #define PIRQG_ROUT 0x6A
58 #define PIRQH_ROUT 0x6B
62 #define COM_DEC 0xE0 /* LPC I/F Comm. Port Decode Ranges */
63 #define LPC_EN 0xE6 /* LPC IF Enables Register */
68 #define SUB_BUS_NUM 0x1A
76 #define PCI_MAST_STS 0x82
78 #define TCOBASE 0x60 /* TCO Base Address Register */
79 #define TCO1_CNT 0x08 /* TCO1 Control Register */
81 /* GEN_PMCON_3 bits */
82 #define RTC_BATTERY_DEAD (1 << 2)
83 #define RTC_POWER_FAILED (1 << 1)
84 #define SLEEP_AFTER_POWER_FAIL (1 << 0)
86 /* IDE Timing registers (IDE_TIM) */
87 #define IDE_TIM_PRI 0x40 /* IDE timings, primary */
88 #define IDE_TIM_SEC 0x42 /* IDE timings, secondary */
91 #define IDE_DECODE_ENABLE (1 << 15)
98 #define I2C_EN (1 << 2)
99 #define SMB_SMI_EN (1 << 1)
100 #define HST_EN (1 << 0)
102 /* SMBus I/O registers. */
103 #define SMBHSTSTAT 0x0
104 #define SMBHSTCTL 0x2
105 #define SMBHSTCMD 0x3
106 #define SMBXMITADD 0x4
107 #define SMBHSTDAT0 0x5
108 #define SMBHSTDAT1 0x6
109 #define SMBBLKDAT 0x7
110 #define SMBTRNSADD 0x9
111 #define SMBSLVDATA 0xa
112 #define SMLINK_PIN_CTL 0xe
113 #define SMBUS_PIN_CTL 0xf
115 #define SMBUS_TIMEOUT (10 * 1000 * 100)
117 #endif /* SOUTHBRIDGE_INTEL_I82801BX_I82801BX_H */