2 * This file is part of the coreboot project.
4 * Copyright (C) 2003 Linux Networx
5 * Copyright (C) 2003 SuSE Linux AG
6 * Copyright (C) 2005 Tyan Computer
7 * (Written by Yinghai Lu <yinghailu@gmail.com> for Tyan Computer)
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 #include <console/console.h>
25 #include <device/device.h>
26 #include <device/pci.h>
27 #include <device/pci_ids.h>
28 #include <pc80/mc146818rtc.h>
29 #include <pc80/isa-dma.h>
31 #include <arch/ioapic.h>
34 #define GPIO_BASE_ADDR 0x00000500 /* GPIO Base Address Register */
38 typedef struct southbridge_intel_i82801ax_config config_t;
40 /* PIRQ[n]_ROUT[3:0] - IRQ Routing (ISA compatible)
41 * 0x00 - 0000 = Reserved
42 * 0x01 - 0001 = Reserved
43 * 0x02 - 0010 = Reserved
49 * 0x08 - 1000 = Reserved
54 * 0x0D - 1101 = Reserved
58 * PIRQ[n]_ROUT[7] - Interrupt Routing Enable (IRQEN)
59 * 0 - The PIRQ is routed to the ISA-compatible interrupt specified above.
60 * 1 - The PIRQ is not routed to the 8259.
69 * Use 0x0ef8 for a bitmap to cover all these IRQ's.
70 * Use the defined IRQ values above or set mainboard
71 * specific IRQ values in your devicetree.cb.
73 static void i82801ax_enable_apic(struct device *dev)
76 volatile u32 *ioapic_index = (volatile u32 *)IO_APIC_ADDR;
77 volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10);
79 /* Set ACPI base address (I/O space). */
80 pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1));
82 /* Enable ACPI I/O range decode and ACPI power management. */
83 pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
85 reg32 = pci_read_config32(dev, GEN_CNTL);
86 reg32 |= (1 << 13); /* Coprocessor error enable (COPR_ERR_EN) */
87 reg32 |= (3 << 7); /* IOAPIC enable (APIC_EN) */
88 reg32 |= (1 << 2); /* DMA collection buffer enable (DCB_EN) */
89 reg32 |= (1 << 1); /* Delayed transaction enable (DTE) */
90 pci_write_config32(dev, GEN_CNTL, reg32);
91 printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32);
94 *ioapic_data = (1 << 25);
98 printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", reg32);
99 if (reg32 != (1 << 25))
102 /* TODO: From i82801ca, needed/useful on other ICH? */
103 *ioapic_index = 3; /* Select Boot Configuration register. */
104 *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */
107 static void i82801ax_enable_serial_irqs(struct device *dev)
109 /* Set packet length and toggle silent mode bit. */
110 pci_write_config8(dev, SERIRQ_CNTL,
111 (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));
112 pci_write_config8(dev, SERIRQ_CNTL,
113 (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0));
114 /* TODO: Explain/#define the real meaning of these magic numbers. */
117 static void i82801ax_pirq_init(device_t dev)
120 config_t *config = dev->chip_info;
122 reg8 = (config->pirqa_routing) ? config->pirqa_routing : PIRQA;
123 pci_write_config8(dev, PIRQA_ROUT, reg8);
125 reg8 = (config->pirqb_routing) ? config->pirqb_routing : PIRQB;
126 pci_write_config8(dev, PIRQB_ROUT, reg8);
128 reg8 = (config->pirqc_routing) ? config->pirqc_routing : PIRQC;
129 pci_write_config8(dev, PIRQC_ROUT, reg8);
131 reg8 = (config->pirqd_routing) ? config->pirqd_routing : PIRQD;
132 pci_write_config8(dev, PIRQD_ROUT, reg8);
135 static void i82801ax_power_options(device_t dev)
141 /* power after power fail */
142 /* FIXME this doesn't work! */
143 /* Which state do we want to goto after g3 (power restored)?
147 pci_write_config8(dev, GEN_PMCON_3, pwr_on ? 0 : 1);
148 printk(BIOS_INFO, "Set power %s if power fails\n", pwr_on ? "on" : "off");
150 /* Set up NMI on errors. */
152 byte &= ~(1 << 3); /* IOCHK# NMI Enable */
153 byte &= ~(1 << 2); /* PCI SERR# Enable */
157 nmi_option = NMI_OFF;
158 get_option(&nmi_option, "nmi");
160 byte &= ~(1 << 7); /* Set NMI. */
165 static void gpio_init(device_t dev)
167 pci_write_config32(dev, GPIO_BASE, (GPIO_BASE_ADDR | 1));
168 pci_write_config8(dev, GPIO_CNTL, GPIO_EN);
171 static void i82801ax_rtc_init(struct device *dev)
177 reg8 = pci_read_config8(dev, GEN_PMCON_3);
178 rtc_failed = reg8 & RTC_BATTERY_DEAD;
180 reg8 &= ~(1 << 1); /* Preserve the power fail state. */
181 pci_write_config8(dev, GEN_PMCON_3, reg8);
183 reg32 = pci_read_config32(dev, GEN_STA);
184 rtc_failed |= reg32 & (1 << 2);
185 rtc_init(rtc_failed);
187 /* Enable access to the upper 128 byte bank of CMOS RAM. */
188 pci_write_config8(dev, RTC_CONF, 0x04);
191 static void i82801ax_lpc_route_dma(struct device *dev, uint8_t mask)
196 reg16 = pci_read_config16(dev, PCI_DMA_CFG);
198 for (i = 0; i < 8; i++) {
201 reg16 |= ((mask & (1 << i)) ? 3 : 1) << (i * 2);
203 pci_write_config16(dev, PCI_DMA_CFG, reg16);
206 static void i82801ax_lpc_decode_en(device_t dev)
208 /* Decode 0x3F8-0x3FF (COM1) for COMA port, 0x2F8-0x2FF (COM2) for COMB.
209 * LPT decode defaults to 0x378-0x37F and 0x778-0x77F.
210 * Floppy decode defaults to 0x3F0-0x3F5, 0x3F7.
211 * We also need to set the value for LPC I/F Enables Register.
213 pci_write_config8(dev, COM_DEC, 0x10);
214 pci_write_config16(dev, LPC_EN, 0x300F);
217 static void lpc_init(struct device *dev)
219 /* Set the value for PCI command register. */
220 pci_write_config16(dev, PCI_COMMAND, 0x000f);
222 /* IO APIC initialization. */
223 i82801ax_enable_apic(dev);
225 i82801ax_enable_serial_irqs(dev);
227 /* Setup the PIRQ. */
228 i82801ax_pirq_init(dev);
230 /* Setup power options. */
231 i82801ax_power_options(dev);
233 /* Set the state of the GPIO lines. */
236 /* Initialize the real time clock. */
237 i82801ax_rtc_init(dev);
240 i82801ax_lpc_route_dma(dev, 0xff);
242 /* Initialize ISA DMA. */
245 /* Setup decode ports and LPC I/F enables. */
246 i82801ax_lpc_decode_en(dev);
249 static void i82801ax_lpc_read_resources(device_t dev)
251 struct resource *res;
253 /* Get the normal PCI resources of this device. */
254 pci_dev_read_resources(dev);
256 /* Add an extra subtractive resource for both memory and I/O. */
257 res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
260 res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
261 IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
263 res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
264 res->base = 0xff800000;
265 res->size = 0x00800000; /* 8 MB for flash */
266 res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
267 IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
269 res = new_resource(dev, 3); /* IOAPIC */
270 res->base = IO_APIC_ADDR;
271 res->size = 0x00001000;
272 res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
275 static struct device_operations lpc_ops = {
276 .read_resources = i82801ax_lpc_read_resources,
277 .set_resources = pci_dev_set_resources,
278 .enable_resources = pci_dev_enable_resources,
280 .scan_bus = scan_static_bus,
281 .enable = i82801ax_enable,
285 static const struct pci_driver i82801aa_lpc __pci_driver = {
287 .vendor = PCI_VENDOR_ID_INTEL,
292 static const struct pci_driver i82801ab_lpc __pci_driver = {
294 .vendor = PCI_VENDOR_ID_INTEL,