2 * This file is part of the coreboot project.
4 * Copyright (C) 2003 Linux Networx
5 * Copyright (C) 2003 SuSE Linux AG
6 * Copyright (C) 2005 Tyan Computer
7 * (Written by Yinghai Lu <yinghailu@gmail.com> for Tyan Computer)
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 #include <console/console.h>
25 #include <device/device.h>
26 #include <device/pci.h>
27 #include <device/pci_ids.h>
28 #include <pc80/mc146818rtc.h>
29 #include <pc80/isa-dma.h>
33 #define GPIO_BASE_ADDR 0x00000500 /* GPIO Base Address Register */
37 typedef struct southbridge_intel_i82801ax_config config_t;
39 /* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
40 * 0x00 - 0000 = Reserved
41 * 0x01 - 0001 = Reserved
42 * 0x02 - 0010 = Reserved
48 * 0x08 - 1000 = Reserved
53 * 0x0D - 1101 = Reserved
56 * PIRQ[n]_ROUT[7] - PIRQ Routing Control
57 * 0x80 - The PIRQ is not routed.
66 * Use 0x0ef8 for a bitmap to cover all these IRQ's.
67 * Use the defined IRQ values above or set mainboard
68 * specific IRQ values in your mainboards Config.lb.
71 static void i82801ax_enable_apic(struct device *dev)
74 volatile uint32_t *ioapic_index = (volatile uint32_t *)0xfec00000;
75 volatile uint32_t *ioapic_data = (volatile uint32_t *)0xfec00010;
77 /* Set ACPI base address (I/O space). */
78 pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1));
80 /* Enable ACPI I/O and power management. */
81 pci_write_config8(dev, ACPI_CNTL, 0x10);
83 reg32 = pci_read_config32(dev, GEN_CNTL);
84 reg32 |= (3 << 7); /* Enable IOAPIC */
85 reg32 |= (1 << 13); /* Coprocessor error enable */
86 reg32 |= (1 << 1); /* Delayed transaction enable */
87 reg32 |= (1 << 2); /* DMA collection buffer enable */
88 pci_write_config32(dev, GEN_CNTL, reg32);
89 printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32);
92 *ioapic_data = (1 << 25);
96 printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", reg32);
97 if (reg32 != (1 << 25))
100 /* TODO: From i82801ca, needed/useful on other ICH? */
101 *ioapic_index = 3; /* Select Boot Configuration register. */
102 *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */
105 static void i82801ax_enable_serial_irqs(struct device *dev)
107 /* Set packet length and toggle silent mode bit. */
108 pci_write_config8(dev, SERIRQ_CNTL,
109 (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));
110 pci_write_config8(dev, SERIRQ_CNTL,
111 (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0));
112 /* TODO: Explain/#define the real meaning of these magic numbers. */
115 static void i82801ax_pirq_init(device_t dev, uint16_t ich_model)
117 /* Get the chip configuration */
118 config_t *config = dev->chip_info;
120 if (config->pirqa_routing) {
121 pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing);
123 pci_write_config8(dev, PIRQA_ROUT, PIRQA);
126 if (config->pirqb_routing) {
127 pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing);
129 pci_write_config8(dev, PIRQB_ROUT, PIRQB);
132 if (config->pirqc_routing) {
133 pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing);
135 pci_write_config8(dev, PIRQC_ROUT, PIRQC);
138 if (config->pirqd_routing) {
139 pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing);
141 pci_write_config8(dev, PIRQD_ROUT, PIRQD);
145 static void i82801ax_power_options(device_t dev)
151 /* power after power fail */
152 /* FIXME this doesn't work! */
153 /* Which state do we want to goto after g3 (power restored)?
157 pci_write_config8(dev, GEN_PMCON_3, pwr_on ? 0 : 1);
158 printk(BIOS_INFO, "Set power %s if power fails\n", pwr_on ? "on" : "off");
160 /* Set up NMI on errors. */
162 byte &= ~(1 << 3); /* IOCHK# NMI Enable */
163 byte &= ~(1 << 2); /* PCI SERR# Enable */
167 nmi_option = NMI_OFF;
168 get_option(&nmi_option, "nmi");
170 byte &= ~(1 << 7); /* Set NMI. */
175 static void gpio_init(device_t dev, uint16_t ich_model)
177 pci_write_config32(dev, GPIO_BASE_ICH0_5, (GPIO_BASE_ADDR | 1));
178 pci_write_config8(dev, GPIO_CNTL_ICH0_5, 0x10);
181 static void i82801ax_rtc_init(struct device *dev)
187 reg8 = pci_read_config8(dev, GEN_PMCON_3);
188 rtc_failed = reg8 & RTC_BATTERY_DEAD;
190 reg8 &= ~(1 << 1); /* Preserve the power fail state. */
191 pci_write_config8(dev, GEN_PMCON_3, reg8);
193 reg32 = pci_read_config32(dev, GEN_STS);
194 rtc_failed |= reg32 & (1 << 2);
195 rtc_init(rtc_failed);
197 /* Enable access to the upper 128 byte bank of CMOS RAM. */
198 pci_write_config8(dev, RTC_CONF, 0x04);
201 static void i82801ax_lpc_route_dma(struct device *dev, uint8_t mask)
206 reg16 = pci_read_config16(dev, PCI_DMA_CFG);
208 for (i = 0; i < 8; i++) {
211 reg16 |= ((mask & (1 << i)) ? 3 : 1) << (i * 2);
213 pci_write_config16(dev, PCI_DMA_CFG, reg16);
216 static void i82801ax_lpc_decode_en(device_t dev, uint16_t ich_model)
218 /* Decode 0x3F8-0x3FF (COM1) for COMA port, 0x2F8-0x2FF (COM2) for COMB.
219 * LPT decode defaults to 0x378-0x37F and 0x778-0x77F.
220 * Floppy decode defaults to 0x3F0-0x3F5, 0x3F7.
221 * We also need to set the value for LPC I/F Enables Register.
223 pci_write_config8(dev, COM_DEC, 0x10);
224 pci_write_config16(dev, LPC_EN_ICH0_5, 0x300F);
227 static void lpc_init(struct device *dev)
229 uint16_t ich_model = pci_read_config16(dev, PCI_DEVICE_ID);
231 /* Set the value for PCI command register. */
232 pci_write_config16(dev, PCI_COMMAND, 0x000f);
234 /* IO APIC initialization. */
235 i82801ax_enable_apic(dev);
237 i82801ax_enable_serial_irqs(dev);
239 /* Setup the PIRQ. */
240 i82801ax_pirq_init(dev, ich_model);
242 /* Setup power options. */
243 i82801ax_power_options(dev);
245 /* Set the state of the GPIO lines. */
246 gpio_init(dev, ich_model);
248 /* Initialize the real time clock. */
249 i82801ax_rtc_init(dev);
252 i82801ax_lpc_route_dma(dev, 0xff);
254 /* Initialize ISA DMA. */
257 /* Setup decode ports and LPC I/F enables. */
258 i82801ax_lpc_decode_en(dev, ich_model);
261 static void i82801ax_lpc_read_resources(device_t dev)
263 struct resource *res;
265 /* Get the normal PCI resources of this device. */
266 pci_dev_read_resources(dev);
268 /* Add an extra subtractive resource for both memory and I/O. */
269 res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
272 res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
273 IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
275 res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
276 res->base = 0xff800000;
277 res->size = 0x00800000; /* 8 MB for flash */
278 res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
279 IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
281 res = new_resource(dev, 3); /* IOAPIC */
282 res->base = 0xfec00000;
283 res->size = 0x00001000;
284 res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
287 static struct device_operations lpc_ops = {
288 .read_resources = i82801ax_lpc_read_resources,
289 .set_resources = pci_dev_set_resources,
290 .enable_resources = pci_dev_enable_resources,
292 .scan_bus = scan_static_bus,
293 .enable = i82801ax_enable,
296 static const struct pci_driver i82801aa_lpc __pci_driver = {
298 .vendor = PCI_VENDOR_ID_INTEL,
302 static const struct pci_driver i82801ab_lpc __pci_driver = {
304 .vendor = PCI_VENDOR_ID_INTEL,