2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 #include <console/console.h>
23 #include <device/device.h>
24 #include <device/pci.h>
25 #include <device/pci_ids.h>
26 #include <pc80/isa-dma.h>
27 #include <pc80/mc146818rtc.h>
28 #include <arch/ioapic.h>
31 static void enable_intel_82093aa_ioapic(void)
36 volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR);
37 volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10);
40 dev = dev_find_device(PCI_VENDOR_ID_INTEL,
41 PCI_DEVICE_ID_INTEL_82371AB_ISA, 0);
44 reg16 = pci_read_config16(dev, XBCS);
45 reg16 |= (1 << 8); /* APIC Chip Select */
46 pci_write_config16(dev, XBCS, reg16);
48 /* Set the IOAPIC ID. */
50 *ioapic_data = ioapic_id << 24;
52 /* Read back and verify the IOAPIC ID. */
54 reg32 = (*ioapic_data >> 24) & 0x0f;
55 printk(BIOS_DEBUG, "IOAPIC ID = %x\n", reg32);
56 if (reg32 != ioapic_id)
57 die("IOAPIC error!\n");
60 static void isa_init(struct device *dev)
64 /* Initialize the real time clock (RTC). */
68 * The PIIX4 can support the full ISA bus, or the Extended I/O (EIO)
69 * bus, which is a subset of ISA. We select the full ISA bus here.
71 reg32 = pci_read_config32(dev, GENCFG);
72 reg32 |= ISA; /* Select ISA, not EIO. */
73 pci_write_config16(dev, GENCFG, reg32);
75 /* Initialize ISA DMA. */
80 * Unlike most other southbridges the 82371EB doesn't have a built-in
81 * IOAPIC. Instead, 82371EB-based boards that support multiple CPUs
82 * have a discrete IOAPIC (Intel 82093AA) soldered onto the board.
84 * Thus, we can/must only enable the IOAPIC if it actually exists,
85 * i.e. the respective mainboard does "select IOAPIC".
87 enable_intel_82093aa_ioapic();
91 static void sb_read_resources(struct device *dev)
95 pci_dev_read_resources(dev);
97 res = new_resource(dev, 1);
100 res->limit = 0xffffUL;
101 res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
103 res = new_resource(dev, 2);
104 res->base = 0xff800000UL;
105 res->size = 0x00800000UL; /* 8 MB for flash */
106 res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
108 res = new_resource(dev, 3); /* IOAPIC */
109 res->base = IO_APIC_ADDR;
110 res->size = 0x00001000;
111 res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
114 static const struct device_operations isa_ops = {
115 .read_resources = sb_read_resources,
116 .set_resources = pci_dev_set_resources,
117 .enable_resources = pci_dev_enable_resources,
119 .scan_bus = scan_static_bus, /* TODO: Needed? */
121 .ops_pci = 0, /* No subsystem IDs on 82371EB! */
124 static const struct pci_driver isa_driver __pci_driver = {
126 .vendor = PCI_VENDOR_ID_INTEL,
127 .device = PCI_DEVICE_ID_INTEL_82371AB_ISA,
130 static const struct pci_driver isa_SB_driver __pci_driver = {
132 .vendor = PCI_VENDOR_ID_INTEL,
133 .device = PCI_DEVICE_ID_INTEL_82371SB_ISA,