2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #ifndef SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H
22 #define SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H
24 #if !defined(ASSEMBLY)
25 #if !defined(__PRE_RAM__)
28 #include <device/device.h>
31 void i82371eb_enable(device_t dev);
32 void i82371eb_hard_reset(void);
37 /* If 'cond' is true this macro sets the bit(s) specified by 'bits' in the
38 * 'reg' variable, otherwise it clears those bits.
41 * reg16 = ONOFF(conf->ide0_enable, reg16, (1 << 5));
42 * reg16 = ONOFF(conf->ide0_enable, reg16, (FOO | BAR));
44 /* TODO: Move into some global header file? */
45 #define ONOFF(cond,reg,bits) ((cond) ? ((reg) | (bits)) : ((reg) & ~(bits)))
47 #define XBCS 0x4e /* X-Bus chip select register */
48 #define GENCFG 0xb0 /* General configuration register */
49 #define RC 0xcf9 /* Reset control register */
52 #define IDETIM_PRI 0x40 /* IDE timing register, primary channel */
53 #define IDETIM_SEC 0x42 /* IDE timing register, secondary channel */
54 #define UDMACTL 0x48 /* Ultra DMA/33 control register */
55 #define UDMATIM 0x4a /* Ultra DMA/33 timing register */
58 #define SMBBA 0x90 /* SMBus base address */
59 #define SMBHSTCFG 0xd2 /* SMBus host configuration */
61 /* Power management (ACPI) */
62 #define PMBA 0x40 /* Power management base address */
63 #define PMREGMISC 0x80 /* Miscellaneous power management */
65 #define PM_IO_BASE 0xe400
68 #define EXT_BIOS_ENABLE_1MB (1 << 9) /* 1-Meg Extended BIOS Enable */
69 #define EXT_BIOS_ENABLE (1 << 7) /* Extended BIOS Enable */
70 #define LOWER_BIOS_ENABLE (1 << 6) /* Lower BIOS Enable */
71 #define WRITE_PROTECT_ENABLE (1 << 2) /* Write Protect Enable */
72 #define SRST (1 << 1) /* System Reset */
73 #define RCPU (1 << 2) /* Reset CPU */
74 #define SMB_HST_EN (1 << 0) /* Host Interface Enable */
75 #define IDE_DECODE_ENABLE (1 << 15) /* IDE Decode Enable */
76 #define DTE0 (1 << 3) /* DMA Timing Enable Only, drive 0 */
77 #define DTE1 (1 << 7) /* DMA Timing Enable Only, drive 1 */
78 #define PSDE0 (1 << 0) /* Primary Drive 0 UDMA/33 */
79 #define PSDE1 (1 << 1) /* Primary Drive 1 UDMA/33 */
80 #define SSDE0 (1 << 2) /* Secondary Drive 0 UDMA/33 */
81 #define SSDE1 (1 << 3) /* Secondary Drive 1 UDMA/33 */
82 #define ISA (1 << 0) /* Select ISA */
83 #define EIO (0 << 0) /* Select EIO */
84 #define PMIOSE (1 << 0) /* PM I/O Space Enable */
86 #endif /* SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H */